Design Engineer

CURRICULUM VITAE

MURGESH

Cell: 874-***-****

Email: *********@*****.***

CAREER OBJECTIVE

Intend to work in a semiconductor industry that utilizes my skills to the fullest extent for the development of the Company as well as growth for individual.

EXPERIENCE/TRAINING

* Having 10 months of work experience from “RV-VLSI DESIGN CENTER”,Bangalore as a Trainee Design engineer from July 2012 to May 2013.

ACADEMIC QUALIFICATION

* POST GRADUATION in VLSI/ASIC Design from RV-VLSI DESIGN CENTER, Bangalore.

* B.E/B.TECH in ELECTRONICS & COMMUNICATION from VIVEKANAND INSTITUTE OF TEECHNOLOGY, Bangalore, with 65.66%.

* PUC FROM KLE’S RLS PU COLLEGE, Belgaum WITH 72.32%.

* SSLC FROM SRI RAMAKRISHNA VIDYASHALA, Mysore WITH 87.36%.

SKILL SET

* Complete knowledge on CMOS fundamentals

* Complete Knowledge of ASIC design flow (RTL TO GDSII).

* Synthesis (Translation, Optimization, Mapping) tools used (Design Compiler)

* Static Timing analysis (STA) tools used (Prime Time)

* Physical Design (Floor planning, Placement, CTS, Routing)

* Low Power Techniques

* Basic Knowledge on PROTOCALS like AMBA AHB/AXI

*

CAD SKILLSET: (EDA TOOLS)

* RTL Design & Verification : QuestaSim / Modelsim

* RTL Synthesis : Synopsys - Design Complier

* Timing Analysis (STA) : Synopsys - Prime Time Suite

* Full Custom tools : Mentor Graphic

IC Station (Schematic & Layout Editor)

Calibre( DRC, LVS, PEX )

* Physical Design Tools : Synopsys - IC Compiler, Magma- Talus

CORE COMPETENCY

STATIC TIMING ANALYSIS (STA) AND SYNTHESIS

* Appreciation of pre and post placement and routing, STA (back annotation).

* Good knowledge of cmos operation

* Knowledge of standard cell library files, timing information, PVT corners, and wire load models, technology files

* Evaluation of slack on all four types of timing paths.

* Analysis of timing reports, slack violations and the rectification of the timing violations by cell resizing.

PHYSICAL DESIGN & VERIFICATION

* Complete Knowledge of ASIC design flow(RTL TO GDSII).

* Appreciation of the challenges faced during Floorplanning, such as macro orientation, Power planning, IR-DROP analysis, Congestion and blockages

* Understanding of Placement with respect to timing closure, Timing optimization and low congestion.

* Importance of clock tree synthesis(CTS)and skew engineering for timing closure.

* Routing flow, parasitic extraction (PEX), Cross talk analysis and back annotation, EM-analysis, ECO and physical verification.

* Design for manufacturability (DFM) constraints to maximize yield.

* Formal verification and physical verification

FULL CUSTOM DESIGN/LAYOUT

* Worked on 90nm and 180nm cmos process based designs.

* Extraction of design specific information for a given block from the design rule constraints, and ability to rectify DRC and LVS errors.

* Ability to verify designs using back annotation (using spef,sdc).

* Layout of devices according to standard cell architecture.

* Basic knowledge of PDK.

IT/TECHNICAL SKILLS:

* Basic knowledge on scripting languages like Tcl, perl.

* Proficient with Windows, DOS and Basic commands in UNIX.

PROJECTS

1: PHYSICAL DESIGN OF HIREACHIAL BLOCK : CSW

Description: The project was aimed at Physical Design and Block-level Implementation of CSW which consists of 56 Macros and 1.5 lacks cells.

Work Done: The design involves 1.5 lacks gates and 56 macros operating at 800MHz. The design starts with creation of the Floorplan followed by placement of macros. Then power planning was done until IR drop less than 5% of VDD was achieved. The next stepinvolves reading scan chains and placement of standard cells and timing optimization. The next step involves clock tree synthesis and optimization. The next step involves clock routing followed by signal routing with crosstalk reduction enabled and post route optimization to fix timing and design rule constraint violations. The next step involves metal filling, spreading and antenna fixing. The final step involves the signoff driven optimization using Star-RC and Prime-Time to create a design ready for signoff.

2:Physical Design of I2C Block: Block level implementation

3:Physical Design of ORCA: Full chip level implementation

4:Synthesis and Static Timing Analysis

Word Done: Gate level Synthesis of various Verilog designsusing Design Compiler and Timing analysis on the generated Netlists.Understanding the effect of RTL coding constructs on generated Netlists and analyzing it.Knowledge of Standard Cell Library files, PVT corners and Wire Load Models. Evaluation of Slack on all four types of timing paths and analysis of timing reports.Fixing of timing violations by cell resizing and logic restructuring.

PROJECTS

1. Design of Inverter Layout:

Description: The project was focused on anIntroduction to Schematic and Layout editor. It was designed according to given specification. Conducted study of inverter for different drive-strengths and loads. DRC, LVS and Parasitic Extraction.

Gained knowledge about purpose of different layers used in the fabrication process as well as delay variation depending on supply voltage, transistor-sizing and output-load.

2. Design of Standard Cells:

Description: To design and characterization of 90nm standard cells like NOT,NAND and NOR with different drive strengths and verification of standard cells by DRC, LVS and PEX.

Challenges Faced: Deciding the width of NMOS and PMOS transistors to meet the standard cell size, the issues of standard cells size is resolved by TransistorFolding technique.

PERSONAL SKILL

* Good problem solving and analytical skills

* A depth in handling project designing and implementation at academic level.

* Excellent team player with abilities in handling multiple priorities and genuine interest in personal & professional development

DECLARATION

I hereby declare that the above mentioned information is correct up to my knowledge.

MURGESH.I.B.

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