RTL Developer(VLSI)

CURRICULAM VITAE

Specialization : Electronics and Communication Engineering

Objective

MADDINA BALAJI

To acquire a responsible and growth oriented position and challenging environment

in the field of electronics that will utilize and strengthen my skills in extreme for the

Contact Information:

benefit of the organization.

Present Address:

#22, 2nd Cross, 2nd Main Professional Summary

Road, Near Shiva Temple,

Working as Project Engineer in Maxine Tec, Bangalore, since January 2013.

Udaya Nagar, Bangalore.

Ph. No : +91-886*******

Knowledge on basic Analog Circuits, Digital Logic Design, SMPS, AC-DC,

Permanent Address: and DC-DC converters.

H no :- 6 -77, Knowledge on RTL Design, FPGA/CPLD implementation, ADC, DAC,

Bayana palle village,

8051 Microcontroller.

Obana palle Post,

Knowledge on Verilog/VHDL HDL language, Embedded C programming,

Rly Kodur Mandal,

Kadapa Dist,

Matlab Simulink, Xillinx ISE and Cadence tools.

Andhra pradesh,

India.

Academic Record

E-Mail:

M.Tech (1st Class) 69.3% Nov, 2012.

*************@*****.***

From Jawaharlal Nehru Technological University Hyderabad, Hyderabad.

Personal Data:

From CVR College of Engineering, Hyderabad.

: 5th Aug 1989

DOB

Specialization in VLSI System Design.

Sex : Male

Nationality : Indian

Marital Status: Single B.Tech (Distinction) 70.1% May, 2010.

From Jawaharlal Nehru Technological University Ananthapur, Ananthapur.

Hobbies:

From C R Engineering College, Tirupathi.

Watching TV, Listening to

Music. Specialization in Electronics and Communication Engineering.

Languages Known:

Intermediate (Distinction) 90.4% March, 2006.

Telugu, English, Hindi

Board of Intermediate Education, Andhra Pradesh.

From Sri Vasistah Jr. College, Rly Kodur.

S.S.C (Distinction) 74.7% March, 2004.

Board of Secondary Education, Andhra Pradesh.

From Victory High School, Rly Kodur.

Projects

Project1 : “RSA Processor Based on High Radix Montgomery Multiplier”

Strengths:

Strong ability for quick Description :

learning.

RTL coding was done by using Verilog HDL.

Hardworking and Simulation and Synthesis were done by using Xillinx 12.4 ISE Design.

Commitment.

Finally, implemented on Xillinx Spartan3 FPGA.

Enthusiastic to learn new

Project2 : “CMOS Digital Polar Modulator for WCDMA Transmitter”

technologies.

Description:

RTL coding using Verilog, Simulation and Synthesis were done b y using

Xillinx 12.4 ISE Design, implemented on Xillinx XC9572XL CPLD.

Project3 : “Design and Implementation of RFID Mutual Authentication

Protocol”

Description:

RTL coding using Verilog, Simulation and Synthesis were done by using

Xillinx 12.4 ISE Design, implemented on Xillinx XC9572XL CPLD.

Project4 : “Monitoring and Controlling of Weather Parameters using Zigbee”

Description:

The wireless weather monitoring system enables to monitor and control the

weather parameters by using Zigbee technology.

Here we monitor temperature, pressure and humidity with the help of sensors.

The data from the sensors are collected by the microcontroller through ADC

and transmitted to the receiver section through wireless medium.

Academic Activities

Paper Presentation on "Row Based Power Gating" at Aakanksha-2k9 C R

Engineering College.

Participated in “Seminar on ASIC Design Verification” organized by CVR College

of Engineering and Shastra Micro Systems.

Declaration

I confirm that the information provided by me is true to the best of my knowledge

and belief.

Place : Bangalore

Date : (M. BALAJI)

Contact this candidate