Design Project
Resume:
ARUNA [pic]
D.No:**-**-*/*/**, Flat No. : FF*,
Sridevi Towers, A.P.S.E.B colony,
Buchirajupalem,
Visakhapatnam- 530027, Email:
*********@*****.***
Andhra Pradesh. Mobile:
Summary of Qualifications
> Good understanding of the ASIC and FPGA design flow
> Experience in writing RTL models in Verilog HDL and Testbenches in
SystemVerilog
> Very good knowledge in verification methodologies
> Experience in using industry standard EDA tools for the front-end
design and verification
VLSI Domain Skills
HDLs : Verilog and VHDL
HVL : SystemVerilog and PSL
Verification Methodologies : Coverage Driven Verification
Assertion Based Verification
TB Methodology : UVM
EDA Tool : Modelsim and ISE
Domain : ASIC/FPGA Design Flow,
Digital Design methodologies
Knowledge : RTL Coding, FSM based design,
Simulation,
Code Coverage,
Functional Coverage, Synthesis,
Static Timing
Analysis, ABV
PROGRAMING LANGUAGE : C,C++
Professional Qualification
Maven Silicon Certified Advanced VLSI Design and Verification course
from Maven Silicon VLSI Design and Training Center, Bangalore
Year: July 2013
Master of Technology, GITAM University, Visakhapatnam, Andhra Pradesh,
India
Discipline: Electrical & Electronics Engineering
Specialization: VLSI Design
Percentage: 78.9% First Class
Year: August 2011
Experience
> March 2013- July 2013, Maven Silicon, VLSI Design and Training Center
> September 2011- June 2012,Assistant Professor in CENTURION UNIVERSITY
in Odhissa.
> Worked in ANURAG-DRDO (Advanced Numerical Research and Analysis
Group, Hyderabad) as Project Trainee from Aug 2010 to April 2011.
VLSI Projects
Real Time Clock - RTL design and verification
HDL: Verilog
HVL: SystemVerilog
EDA Tools: Modelsim, Questa - Verification Platform and ISE
> Implemented the Real Time Clock using Verilog HDL independently
> Architected the class based verification environment using
SystemVerilog
> Verified the RTL model using SystemVerilog.
> Generated functional and code coverage for the RTL verification sign-
off
> Synthesized the design
Dual Port RAM - verification
HVL: System Verilog
EDA Tools: Modelsim, Questa - Verification Platform and ISE
> Implemented the Dual Port Ram using Verilog HDL independently
> Architected the class based verification environment using system
Verilog
> Verified the RTL module using System Verilog
> Generated functional and code coverage for the RTL verification sign-
off
Router 1x3 - RTL design and Verification
HDL: Verilog
HVL: SystemVerilog
EDA Tools: Modelsim, Questa -- Verification Platform and ISE
Description : The router accepts data packets on a single 8-bit port called
data and routes the packets to one of the three output channels, channel0,
channel1 and channel2.
> Architected the design and described the functionality using Verilog
HDL.
> Architected the class based verification environment using system
Verilog
> Verified the RTL model using SystemVerilog.
> Generated functional and code coverage for the RTL verification sign-
off
> Synthesized the design
Academic Project:
> Behavioral Modeling Of High speed Pipelined Analog To Digital
Converter: Description: Design of 14-bit, 100 MSPS, Dual channel
pipelined A/D converter IC can be used for Intermediate Frequency (IF)
Analog Front-End (AFE) in communication systems. Moreover some of the
data acquisition systems also need high speed, high accuracy data
converters where faster data requirements are needed (viz. Ultrasound
sensors etc). In terms of frequency, MDAC is a very critical block to
meet the high sampling requirements of ADC. Unity Gain Bandwidth (UGB)
of the Operational Transconductance Amplifier (OTA) for MDAC requires
high fT for the transistor. UMC 130nm is preferable technology to meet
100 MSPS speed and possible scale up of sampling frequency for future
versions. Hence this IC is being designed using UMC 0.13- CMOS
technology. The converter is implemented with 6 stage pipeline
architecture. The design is based on switch-capacitor circuitry. Each
stage consists of a residue OTA, differential comparators (sub-ADC)
and a sub-DAC. The converter accepts +/- 1V fully differential signal
up to 100MHz. The digital output from every stage is digitally
corrected to obtain a 14+1 bit (Extra sign bit) final output.
Tools used: MATLAB & CADENCE.
> UART:
Description: Most computers and microcontrollers have one or more
serial data ports used to communicate with serial input/output devices
such as keyboards and serial printers. By using a modem connected to a
serial port, serial data can be transmitted to and received from a
remote location via telephone lines. The serial communication
interface, which receives and transmits serial data.
Tools used: Xilinx.
> HOME AUTOMATION USING ZIGBEE TECHNOLOGY:
Description: The objective of the project is working model of the
Zigbee technology. Through this project we learn the wireless
communication using Zigbee module. In this project we took a simple
application of automating different home appliances.
Tools used: Keil C
Industrial Training
Undergone 15 days Vocational Industrial Training on Telecommunications in
Visakhapatnam Steel Plant, Visakhapatnam
Presentations
. K.ARUNA, " Behavioral Modeling Of High Speed Pipeline ADC's ",
International Conference on Machine Intelligence Application to Power,
Signal Processing, Communication and Control (MIPSCCON-2011),COM, pp
99-104, 7th -9th April,2011.
Personal Profile
Name : K.ARUNA
Father's Name : Sri K.CH.ABBULU
Date of Birth : 05th August 1987
Nationality / Religion : Indian - Hindu.
Marital Status : Unmarried.
Languages Known : English, Telugu and Hindi.
Declaration:
I hereby declare that the above details are correct and complete to the
best of my knowledge and belief.
Place: Visakhapatnam
Date: / / 2013
(Kukkala. Aruna)
Contact this candidate