Engineer Design

Bharath Bhushan H

Mob: 895******* E mail:

**********@*****.***

***************@*****.***

Objective

To Become a Successful Professional in the field of VLSI Technology and to Work in

innovative and Competitive world

Personal summary

Have over 3+year’s experiences in Verilog coding, FPGA design and verification. I have

worked as a RTL design engineer involved in verification, synthesis and validation on Xilinx

FPGA. Now I am exposed to UVM methodology for AXI verification.

Employment Details (3+ Years)

Working as a Design and Verification engineer at SeviTech Systems pvt.ltd,

•

Bengaluru from September 2013 till now.

As a Design and Verification engineer at Techscope solutions Bengaluru from August

•

2010 to September 2013.

Technical Skills

• VLSI CAD Tools

• Mentor Graphics Tool Suite (Modelsim/Questa)

• Synopsys VCS Simulator.

• Xilinx tool for FPGA (ISE 14.3)

• HDL Languages: Verilog, System Verilog (beginner), UVM (beginner).

• Protocols: AMBA (APB, AHB, AXI4, UART, VGA, I2C, MDIO, SPI, Interlaken, SerDes.

• Algorithm: AES,RSA, CORDIC

• Memories: cache(beginner)

• Scripting Language: Perl (beginner).

• Operating system: Windows, Linux.

• Knowledge in Xilinx Spartan 6 kit and Spartan 3E kit.

Educational Qualification

B.E in Electronics and communication

•

In 2010 from Dr. T. Thimmaiah Institute of Technology, KGF, Kolar

Diploma in Electronics and communication

•

In 2007 from MN Technical Institute, kammagondanahalli, Jalahalli, Bengaluru

Projects Details

1. Title: Design and Verification of Interlaken protocol (ongoing).

Center: SeviTech Systems, Bengaluru.

Responsibilities:

Designing Interlaken

•

• Prototyping on FPGA

Title: Design and Verification of MDIO protocol with APB master interface

2.

Center: SeviTech Systems, Bengaluru.

Responsibilities:

Designing MDIO Master and Slave

•

Designing APB master

•

Writing testcases and BFM(Bus

• Functional Model) using Verilog tasks

• Prototyping on FPGA

Title : Design and Verification of SPI Master controller

3.

Center: Techscope Solutions, Bengaluru.

Responsibilities:

Designing SPI master and Slave

•

Writing test cases and BFM(Bus

• Functional Model) using Verilog tasks

• Prototyping on FPGA

Title: Design and Verification of Asynchronous AXI Master and Slave.

4.

Center: Techscope Solutions, Bengaluru.

Responsibilities:

Designing AXI read write transitions

•

Writing test cases and BFM(Bus

• Functional Model) using Verilog tasks

• Prototyping on FPGA

Title: Design and Verification of AXI DMA lite.

5.

Center: Techscope Solutions, Bengaluru.

Responsibilities:

Designing AXI read write transitions

•

Designing DMA Controller

•

Writing test cases using

• Verilog tasks

• Prototyping on FPGA.

Title: Design and Verification of APB based I2C controller.

6.

Center: Techscope Solutions, Bengaluru.

Responsibilities:

Designing APB master and slave

•

Designing I2C protocol with FS mode

•

Writing test cases and BFM(Bus

• Functional Model) using Verilog tasks

to verify the APB access with I2C

• Prototyping on FPGA

Personal Details

Date of Birth : 14 11 1988

Sex : Male

Nationality : Indian

Marital Status : Single

Languages

Known : English,kannada

Permanent Address:

#100, Gavipuram H.B.S

2nd stage, behind Jnanabharathi

L ayout 2nd stage,

Bengaluru-560056

Declaration

I here by declare that the above information given by me is true to the best of my Knowledge.

Place: Bengaluru Bharath Bhushan H

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