Electrical Engineer Design

Varun Parmar

****, * ****** ***, *****, AZ ********@***.*** www.linkedin.com/in/varunparmar/

Mobile: 480-***-****

Electrical Engineer pursuing masters in mixed signal VLSI design. Innovative and very passionate for mixed signal circuit design. Have hands on

experience with lower technology nodes and basic understanding of design flow.

EDUCATION

Master of Science, Electrical Engineering Arizona State University, Tempe, AZ Dec 2013 GPA 3.32

Bachelor of Science, Electronics Engineering RGPV Bhopal, INDIA May 2011 GPA 3.5

INTERNSHIP EXPERIENCE

Indian Institute of Technology, Bombay, India, Cadence 65nm ST Micron Jun-Dec’ 12

• Studied clock and data recovery circuits for high speed (~40Gbps) off/on chip serial interconnects.

• Literature study on flip-flops, phase detectors and analyzed them by building macro models to get a behavioral understanding.

• Designed transistor level phase frequency detector for periodic signals and optimized dead zone problem.

• Designed current mode logic flip flop in Cadence Spectre, parasitic extraction in Calibre, layout in Virtuoso Layout Editor.

• Flip flop characterized with noisy supply, jittery clock and data, optimized layout of flip flop at 33 Gbps data rate, 4.5mW power.

ACADEMIC PROJECTS

12 bit 80 MHz Pipeline Analog to Digital Converter, Cadence Spectre and Matlab, TSMC 0.18µm, Spring 2013, (Under Dr. Garrity)

• Modelling of 9bit RSD ADC in Matlab and simulation of entire ADC (9-bit RSD and 3-bit flash ADC) in Cadence Spectre.

• 1.5bit/stage RSD was designed with flip around MDAC stage consisting of an amplifier, two comparators, and a digital circuitry.

• Alignment and synchronization of outputs from each RSD stage using D flip-flops, adding overlapped bits with 3bit flash ADC.

• Priority encoder [8:3] designed to convert thermometer code to binary code in 3bit flash.

• Consistent SNDR in the entire input bandwidth of 39Mhz was observed.

• Validated ADC with full swing sine wave near maximum input frequency and a fixed DC value input.

Rail to Rail Differential Amplifier, Cadence Spectre, TSMC 0.25µm, Spring 2012 (Under Dr. Bakkaloglu)

• Realized high input range common mode amplifier with P and N MOS differential pairs, PMOS pair worked on low input levels and NMOS pair on

high input levels.

• AC and transient simulation for analysis of these parameters: PSRR+, PSRR-, CMRR and slew rate.

• Accomplished design for: 40dB DC gain; 80 MHz unity gain frequency; 1mW power; for entire input range of [0.2-2.8V], 1pF load.

CMOS β -Multiplier current Reference, Cadence Spectre, TSMC 0.25µm, Spring 2012 (Under Dr. Bakkaloglu)

• Designed CMOS β multiplier based constant ‘gm’ current reference circuit to generate supply independent biasing along with startup circuitry.

• Two different designs consisted of cascode topology and in-built amplifier was implemented.

• Mismatch in currents were kept within +/- 5% limits, examined constant ‘gm’ across -20 C to 85 C.

Operational trans-conductance amplifier, Cadence Spectre, TSMC 0.25µm, Spring 2012 (Under Dr. Bakkaloglu)

• Designed OTA with 55dB gain, 55Mhz UGBW, input thermal noise floor of 10nV/sqHz, 1.6mW power dissipation, 2.3V output swing.

• OTA driving common source amplifier gave better gain, prone to un-stability, compensated with a capacitor and cancelled zero with a resistor.

• Layout using common centroid method to reduce variations across the die and increasing area for better matching.

Folded cascode amplifier, Cadence Spectre, TSMC 0.25µm, Spring 2012 (Under Dr. Bakkaloglu)

• Designed folded cascade amplifier with class AB output buffer capable of driving parallel load of 50ohm and 200pF.

• The unity gain frequency was 5 MHz and slew rate 10 V/μs was achieved for a load of 1 pF.

• Output swing of 1V peak to peak was achieved, noise floor of 8.7nV/sqrtHz.

Asynchronous FIFO, Modelsim, Spring 2013 (Under Dr. Gilsdorf)

• Implemented parameterized FIFO memory with read/write mechanisms in Verilog.

• Functional modules for synchronization between clocks of different frequency domain were built.

• Validation of FIFO was done using Verilog test benches, later verified by system Verilog test benches.

TECHNICAL SKILLS and RELEVANT COURSES

CAD Tools: Cadence ICFB, Virtuoso, Spectre, Mentor graphics (ModelSim, Calibre (xRC, Design Rule Check, Layout V/s Schematic))

Languages: C, Matlab, Verilog.

Courses: Semiconductor Device Physics, Analog IC Design, Advanced Analog IC Design, Digital IC Design, VLSI Design,

Advanced Hardware System Design, Advanced Power Electronics, Nyquist Rate Analog to Digital Converters.

Skills: Transistor level analog/mixed signal circuit design and analysis using Cadence (Analog Design Environment and Virtuoso Layout

Editor). Decent knowledge of amplifiers, phase frequency detector, band-gap references, DC-DC converters, CMOS logic family,

static and dynamic implementation, combinational and sequential logic constructs, timing analysis, verification and debug.

TEACHING ASSISTANT, W.P.C School of Business, Arizona State University Aug 2011-Present

- Assist undergraduate students with their course problems, MGT 300 course, Mastering Self Leadership.

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