Engineer Software

R OO PAS HR E E KU L KA R NI

WORK EXPERIENCE: * YEAR IN IT INDUSTRY.

Email: ***********@**********.***

Phone: 990*******

Address: B4-109,Gokulam apartments, Kanakapura road, Bangalore

Education:

Bachelor of Engineering in Electronics and Communication from Karnatak University, 2001, 70.5%

SSLC with 87.4% and PUC with 75.7% scores.

Additional courses:

VLSI Design Certification from Sandeepani school of vlsi design Bangalore, India. 4 months.

Followed by six months as trainee at CG-CoreEl Programmable solutions.

Deutsche(German) for Beginners, 100 hours training in Deutsche, Volkschoschule (VHS)

Düsseldorf, Germany, Oct 05- Dec 05

Skills:

Languages: VHDL, Verilog, C,Core Java

PROJECTS:

1)ETHERNET TRANSMITTER:

Worked as a software engineer in GL communications, bangalore for 3 months from july2011 to

sep2011.

Design of Ethernet transmitter in VHDL and written testbench to verify it.

2)ON BOARD PROCESSOR MK-III BASED ON 486 PROCESSOR

Trainee engineer in AutoTec systems,Bangalore from Aug 2003 – Jan 2004

On board processor is a Real time control system capable of handling higher resolution

mathematical operations for functions of guidance and control of missile checkout, mission

sequencing and telemetry data generation. The OBP is the brain for the control and command of the

missile both for pre-flight and in-flight operations. I was responsible for coding in VHDL,Interface

signals for Telemetry data generation and Command Guidance Unit (CGU), this was implemented

using WARP (Cypress WARP tool), Schematic design using ORCAD tool. Selection of electronic

components,Preparing corresponding documents (Bill Of Materials, drawing),Netlist generation and

checking, Timing analysis, Power analysis and Board verification.

3)TITLE: HIGH PERFORMANCE 1024-POINT COMPLEX FFT PROCESSOR

Trainee engineer in Sandeepani school of vlsi design, CG-CoreEl programmable solutions from

Aug 2002 – Jan 2003

This processor computes a 1024-point complex forward FFT or Inverse FFT (IFFT). The FFT

processor engine is developed for Virtex-2 family of Field Programmable Gate Arrays (FPGAs).

The FFT engine employs Cooley-Tukey radix-2 decimation-in-time (DIT) FFT algorithm to

compute the DFT of a complex sequence and the concept of in-place computation to optimize

memory usage. The algorithm permits an efficient realization of hardware and faster memory access

speed with lower power consumption. In order to operate the processor, data must be first loaded

into the internal memory usage. The processor is then instructed to compute the FFT, overwriting

the input data in the RAM with the results (Inplace Computation). Upon completion of the FFT, the

results may be read out from the RAM via the output data port. (Dual Port RAM). The project is

targeted to FPGA, which follows the Direct Mapping technique for the implementation.

A Register Transfer Logic (RTL) coding and Functional verification is performed targeting Virtex-2

device family FPGA, We also used XtremeDSP Design Flow (Matlab / Simulink) environment for

Modelling.RTL coding in VHDL, Test vector generation using HDL Bencher, synthesis and

Implementation.

4) TITLE : MODELING AND SIMULATION OF MICROPROGRAM SEQUENCER.

SDM College of Engineering & Technology, Dharwad of 5 months duaration

Am2910A is an address sequencer intended for controlling the sequence of microinstructions stored

in microprogram memory. Besides sequential access, it provides conditional branching to any

microinstruction within 4096 micro-word range. A last-in first-out stack provides microinstruction

subroutine linkage and looping capability. There are 9 levels of nesting of micro-subroutine.Test

bench was written to verify the design.

Wrote a booklet “Learning Deutsche for Kannada Speakers”, August 2005

Whitepaper on “Current state of home robotics”, September 2005.'

The above-mentioned information is true & tangible. Any references will be provided on request.

Roopashree Kulkarni

Bangalore

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