Engineer Design

Ph :+91-929*-****-**

Ravi Kiran Bondugula *********.*********@*****.***

Career Objective:

To take up a challenging position as an engineer in a dynamic and result oriented organization that actualizes my qualifications, skills, and abilities.

Summary:

• Strong at Digital Design concepts.

• Working knowledge of Verilog HDL.

• Exposure in debugging FPGA Boards using Chipscope-Pro.

• Familiar with Xilinx FPGA tool flow.

• Good knowledge in DUT Verification using Test benches.

• Adept in end-to-end development of projects from requirement analysis to system study, designing, simulation, synthesis, documentation and implementation.

• Familiar with protocols like AMBA AHB, APB.

• Knowledge in both functional and gate level simulations.

• Have basic working knowledge on MATLAB like XILINX system generator and HDL,C-Code generation using MATLAB.

• Definition of block architecture/design of digital circuits

• Implement design through RTL coding, adhering to quality guidelines

• Knowledge of scripting/language – perl

• Front end design includes RTL, simulation synthesis

• Knowledge of Microprocessor Architecture

• Knowledge on perl scripting .

• Knowledge on manual testing .

• Hands of experience in programming with C-Language.

• Familiar with DSP, Matlab

Educational Qualifications:

• M.Tech in VLSI System Design

In A Vijaya institute Technological Research Academy, JNTU Hyderabad.

Percentage – 82%

• B.Tech in Electronics and Communication Engineering – June 2011

AURORA engineering college,Hyderbad

Aggregate-71.58%

• Intermediate (MPC stream- May, 2007)

Aggregate-92.3%

• Secondary Eduction (March 2005)

Aggregate-85.66%

Work experience:

• Working as Design Engineer in Blue Chip Technologies Pvt.Ltd, Hyderabad from Dec 2012 to present.

Role and Responsibilities:

• Digital design for logic, Write HDL (VERILOG / VHDL) code for design.

• Debugging the design, Test bench writing

• Simulation and Synthesis process

• Worked as Design Engineer in Vision Krest Embedded Systems PVT LTD, Hyderabad from June 2011 to Dec 2012.

Role and Responsibilities:

• Digital design for logic, Write HDL (VERILOG / VHDL) code for design.

• Debugging the design, Test bench writing

• Simulation and Synthesis process

Projects:

• Design of an AMBA-Advanced High performance Bus Protocol IP Block

• The AHB (Advanced High-performance Bus) is a high-performance bus in AMBA (Advanced Microcontroller Bus Architecture) family.

• This AHB can be used in high clock frequency system modules. The AHB acts as the high-performance system backbone bus.

• AHB supports the efficient connection of processors, on-chip memories and off-chip external memory interfaces with low-power peripheral macro cell functions.

Environment: VERILOG- FPGA SPARTAN 3E

• A Spurious-Power Suppression Technique for Multimedia/DSP Applications using Verilog HDL,

• (SPST) which can dramatically reduce the power dissipation of combinational VLSI designs for

Multimedia/DSP purposes.

• Debugging using Xilinx ise, chip scope pro, Test bench writing for verification.

• Design, Timing Verification and Synthesis of 32 Bit Pipelined IEEE 754 Single Precision Floating Point Multiplication Unit,

• 32 Bit Floating Point pipelined multiplier is designed using Verilog HDL and is optimized to meet Timing Requirement

• Simulation using Modelsim and synthesis in Xilinx synthesizer

• Low-Power and Area-Efficient Carry Select Adder using Verilog HDL,

• Design csa architecture using Verilog HDL, micro wind tool for layout design

• The results analysis shows that the proposed CSLA structure is better than the regular SQRT CSLA.

• Design of Multiplication Acceleration Through Twin Precision

• Buildup the architecture, modeled by using the VHDL.

• Simulated the top level design using ModelSim 6.4b, The design using Xilinx ISE 14.1 synthesizer.

Tools:

• Mentor Graphics - Model-Sim, Questa sim, I-sim (Xilinx ) for VHDL/Verilog simulation

• Xilinx synthesizer for synthesis process

• Xpower analyser, Place & Route .

• Xilinx tools for FPGA.

• Chip Scope Pro tool for verification

• Xlinx core generator, Matlab

• EDK, SDK

• Micro wind for Layout

Strengths

• Highly innovative,

• Self-motivated,

• Continuous learning quest,

• Ability to work under pressure,

• Efficient.

Personal Profile:

Father’s name : Bondugula Venkatesham

Date of Birth : 11th June 1990

Marital Status : Unmarried

Hobbies : Playing Cricket and Listening Music.

Address : Yusuf guda check post,

Near rehmath nagar,

Hyderabad-500045.

Place :

Date: (RAVIKIRAN.B)

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