Design System
Resume:
PROFILE SUMMARY:
> Overall experience: *.* years of experience at Techscope Solutions
> Competencies: Knowledge and experience in RTL Design/ Verification
EXPERIENCE SUMMARY:
. Part of verification team in AXI4 Protocol
. Designed and Verified APB Protocol
. Designed and Verified AHB Protocol
PROFESSTIONAL EXPERIENCE:
. AXI4 Protocol.
. Designed APB and AHB Protocols.
. Verified the Designed APB and AHB Protocols.
AMBA AXI4:
. The AMBA AXI protocol is high-performance, high-frequency system
designs and includes a number of features that make it suitable for a
high-speed submicron interconnects.
. I have studied the SPEC defined by AMBA.
. Wrote test cases to test the DUT according to SPEC defined by AMBA.
AMBA APB:
. The APB is part of the AMBA 3 protocol family. It provides a low-cost
interface that is optimized for minimal power consumption and reduced
interface complexity. The APB interfaces to any peripherals that are
low-bandwidth and do not require the high performance of a pipelined
bus interface. The APB has unpipelined protocol.
. I have studied the SPEC defined by AMBA and Implemented RTL design for
Master.
. Verified using testbench.
EDUCATIONAL QUALIFICATIONS:
Education Board Institute Marks Year
Mtech (VLSI and
Embedded VTU NCET Bangalore 70.48% 2013
System)
BE Electronics VTU AIET Gulbarga 58.05% 2011
and
Communication
PUC Pre-university SB college 57.16% 2007
board
SSLC CBSE CPEMS 58.06% 2005
TECHNICAL SKILLS
Programming languages C, C++ (basics).MATLAB.
Hardware Description Verilog, VHDL, SV,UVM.
languages
Assembly languages 8051, 8086, msp430, ARM cortex-M3(basic).
Area of Interest Digital Design,Design Verification,Embedded
System,
DSP, RTOS, Design of VLSI system,logic
design,LIC.
Operating systems Windows, Linux.
Tools Cadence (NC Sim, Virtuoso), Modelsim Questa
10.1c, Xilinx. Turbo C/C++,keil C.MATLAB
R2012a.
ACADEMIC PROJECTS
Mtech -Project Title " Efficient and High Through put Implementation of
AMBA AXI to AHB Sychronize Bridge for system on chip applications "
Description- With the transition of new designs to AMBA3 AXI, there is
considerable existing ARM AMBA 2.0, AHB-based intellectual property (IP)
which continues to be very useful. This project is on efficient and high
throughput pipeline based architecture and implementation of AXI to AHB
Bridge which enables the seamless plugging in of AHB slaves to AXI masters.
The AXI is very high through put bus with parallel read/write bus. The
architecture proposed will also provides synchronization clock domain
support from AXI side to AHB side. The testing is performed using system
Verilog based test bench, as assertion based verification done as to ensure
the robust functioning of bridge. The design will also be synthesized for
ASIC and FPGA (Spartan 3E).
Advanced microcontroller bus architecture (AMBA) protocol family
provides metric-driven verification of protocol compliance, enabling
comprehensive testing of interface intellectual property (IP) blocks and
system-on-chip (SoC) designs. AXI4 also includes information on the
interoperability of components. The Advanced High-performance Bus (AHB) is
operated at medium frequency which can be interfaced to low speed
peripherals like SPI, UART. AXI has separate write and read channel but
AHB has only one channel to both read and write operation which makes AXI
bus to operate at twice the speed of AHB.
PERSONAL MEMORANDUM
Date of Birth : 1st Jan 1990.
Father's name : Gurupadappa Wali.
Strengths : Hardwork and patience.
Hobbies : swimming, playing and watching cricket.
Nationality : Indian.
Language : English, Kannada, Hindi.
Address : Sachin Wali.
S/o-Gurupadappa Wali
Plot no:36,pragati colony
Sedam road. Tq-Gulbarga
Dist-Gulbarga pin-585105 Mob-+91-
I declare that the information given above is true to the best of my
knowledge.
Signature
STRENGTHS:
. Hard working, capable to mingle quickly
. Quick learner
. Dedication
. Motivating and Leading Abilities
. Teamwork
PERSONAL DETAILS:
. Nationality : Indian
. Sex : Male
. Marital Status : Single
. Languages Known : Kannada, English, Hindi
. Father's Name : Gurupadappa Wali
. Date of Birth : 19-01-1990
DECLARATION:
I hereby declare that the information furnished above is true to the best
of my knowledge.
Place: Bangalore Sachin Wali.
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