Project Engineer

RESUME

Prasad barki

Contact: 888-***-****

E-mail: ****.*.******@*****.***

OBJECTIVE:

Seeking as Design or Verification engineer position in the field of VLSI.

Technical Knowledge

Good understanding of the ASIC and FPGA design flow.

Experience in writing RTL models in Verilog HDL and Testbenches in SystemVerilog.

Experience in using industry standard EDA tools for the front-end design and verification.

WORK EXPERIENCE: (2 year-3 months)

Current Company : Technosoft Development India Pvt Ltd.

Designation : Design & Verification Engineer.

Duration : From OCT 2011 to till date.

EDUCATIONAL PROFILE:

M.Tech in VLSI Design & Embedded Systems with 73.58% VTU Belgaum - 2011.

B.E in Electronics & Communication Engineering with 71% VTU Belgaum - 2009.

TECHNICAL EXPERTISE:

HDL Experience in VHDL, Verilog and System Verilog.

Competent in EDA tools like Xilinx and Modelsim, Questa sim, lattice diamond and Quartus 2.

Good experience in Functional Verification and RTL design.

Competent in Front end digital designs and Verification.

Extensive knowledge of FPGA/ASIC designs and design flow.

Protocol knowledge of I2C, DDR3, AMBA-AXI, AMBA-AHB, AMBA-APB.

Scripting languages: basics of perl.

PROJECT DETAILS: Worked on system verilog project, Design project, Verification project, worked on

LatticeXP2 Brevia2 Evaluation Board.

Projects APB Verification environment in System Verilog.

The APB is part of the AMBA 3 protocol family. It provides a low-cost interface that is

Description

optimized for minimal power consumption and reduced interface complexity.

Contribution Creating the verification environment to APB.

Tools-used Questa-sim10.0b.

Projects Lattice Diamond Environment

Description Displaying the stop-watch valve, Displaying the counter and shift valve,

converting ascii valve to hexa decimal valves.

Contribution Designed the clock logic, input logic, switch logic, display logic, output

logic for some designs.(e.g : 1)Pedometer 2)Count-shift logic 3) Alu 4)

Ascii to Hexa converter)

Tools-used Lattice Diamond and LATTICE-XP2 (device LFXP2-5E) board.

project DDR3 RAM verification

description Processor communicates with the AXI and APB to give the commands and

address for read and write to the DDR3 memory using the DDR3 memory

controller.

contribution Observing the communication between ddr3 controller and ddr3 memory

through protocol moniter. And checking the different sequences.

Tools-used Modelsim, Xilinx

project Amba-AXI verification

description Processor uses the amba master bus to communicate with some memories and

pheripherals.AXI is having different channels for read address and write address

so communicating is faster using this protocols.

contribution Verified using axi-slave bus function model, generated protocol monitor to

observe transfers between master and slave, created whole test bench

environment.

Tools-used Modelsim

project DESIGN OF GENERIC INTERRUPT CONTROLLER

description The generic interrupt controller is an IP which will handles the peripheral

interrupts. The IP supports the AMBA-AHB bus protocol .The IP will supports

up to 1024 interrupts. The peripheral devices may be I 2C, UART, SPI or any

other devices. Any of these devices wants to send interrupts to the processor, it

is possible through GIC. GIC will process the interrupt signals sent by the

peripheral devices and send it to the processor. GIC supports generation of

maskable and non-maskable interrupts (MI and NMI) for each processor.

contribution Design of interrupt controller slave using the amba-AHB protocol. Designed

address decoder, data controller, register sets, interrupt controller blocks.

Tools-used Xilinx

project Amba-APB verification

The APB is part of the AMBA 3 protocol family. It provides a low-cost interface that is

description

Optimized for minimal power consumption and reduced interface complexity. Every transfer

takes at least two cycles.

contribution Master bus function model, slave bus function model, protocol monitor bfm

and test bench generation.

Tools-used Questa sim 6.0.

project Amba-AHB verification

AHB is a new generation of AMBA bus which is intended to address the requirements

description

of high-performance synthesizable designs. It is a high-performance system bus that

Supports multiple bus masters and provides high-bandwidth operation.

contribution Master bus function model, protocol monitor bfm and test bench generation.

Tools-used Modelsim

DESIGN & VERIFICATION OF I2C

project

The I2C designed is of minimum no of LUT’s or gates. This I2C designed here is

description

Independent of any IP cores. The design consists of creating different registers

like prescale register, command register, transmit register, receive register and

generation of different signals like start, stop, read, write.

Design of I2C master FSM based design and simple test bench generation.

contribution

Tools-used Xilinx

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