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C, C++

Location:
Bangalore, KA, India
Posted:
December 13, 2013

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Resume:

CURRICULUM VITAE

Name : CHAITHRIKA E-mail : ****************@*****.***

Address : D/o P.N.Gopalarishna Bhat Contact number : 872-***-****

‘Brindavana Nivasa’, Andar (P)

Karkala (T), Udupi (D)

PIN: 574 101

Objective:

To achieve a challenging position in the technical profession that will enable me to prove

my technical skill, offers professional growth while being innovative and flexible.

Academic details:

Education Year of % of School/college Board/University

passing marks

B.E in 2013 71.80 S.J.C.Institute of VTU

Telecommunication Technology,

Chickballapur

PUC 2009 70.00 Sri Bhuvanendra PU Board,

PU College, Karnataka

Karkala

SSLC 2007 93.28 Govt.High Karnataka

School,Shirlalu Secondary

Karkala(T) Education Board

Personal Strengths:

Quick learner, self confidence, passionate about work.

Ability to work in a team, high aspirations.

Technical Skills:

Programming : C, C++, Java, VHDL

Other : Wireless communication, Embedded Systems, Computer

Communication Networks, Fundamentals of VLSI

Languages known:

Kannada, English, Tulu

Hobbies/Interest:

Reading story books, magazines, cooking, listening music.

Tour/Travelling. Playing games.

Technical Participations:

Successfully completed AutoBotz on 8051, a course on fundamentals of Autonomous

Robotics conducted by Technophilia Systems.

Participated in vocational training on Computer Communication Networks and Internet,

held at RTTC Mysore.

Participated in National level Paper Presentation competition ‘KSHITIJA – 2013’ held at

SJCIT, Chickballapur.

Academic Project:

“Design and Implementation of Source Synchronous Switch for a Network on Chip”.

Objective : To perform design and implementation of a source synchonous switch to support

guaranteed throughput. A silicon-proven prototype of a 16-bit-data 5-bidirectional-port switch

can accept data from all the five directions.

Tools Used :

Software : XLINX xse – creation and synthesis of Verilog Modules

Modelsim – Simulation of the test bench.

Hardware : FPGA board.

Personal Details:

Name : Chaithrika

Father’s Name : P.N.Gopalakrishna Bhat

11th August 1991

Date of Birth :

Gender : Female

Nationality : Indian

Holding Passport : Yes

I hereby declare that above furnished information are true to the best of my knowledge and

belief.

Date :

Place : Bangalore CHAITHRIKA



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