Development Design

HARISH S SRIDHARA

***** *** ***** **, ***# F**, Fountain Valley CA 92708

408-***-**** ● ******.*.********@*****.***

C OMMUNICATION & N AVIGATION S YSTEMS E NGINEER

Strong experience of GPS-GNSS navigation, cellular technologies of LTE, UMTS, CDMA2000, GSM etc

Strong working knowledge of FPGA hardware and firmware design with soft-core processors and Xilinx tools.

Adept at MATLAB, C, C++ with focus on signal processing and communication systems.

Excited by demands of research and development environment with ability to work independently or in a group. Highly

motivated and analytical with an aptitude for innovative solutions.

Languages C, C++, JAVA, MATLAB, Python, VHDL, Verilog, CUDA

Engineering Tools MATLAB/SimuLink, Xilinx ISE, EDK tools, Android NDK,

LTspice, HSpice, Cadence, ModelSim

Mobile Development Android OS, Linux

E DUCATION & C REDENTIALS

MASTER OF SCIENCE, Electrical Engineering with emphasis on Communications 08/2009

UNIVERSITY OF SOUTHERN CALIFORNIA (USC), Los Angeles, CA

GPA - 3.71/4

BACHELOR OF ENGINEERING, Electronics and Communication Engineering 05/2007

MANIPAL INSTITUTE OF TECHNOLOGY, Manipal, India

GPA – 9.44/10

E XPERIENCE

Quantum Dimension, Inc., Huntington Beach, CA 02/2010 - Present

Communication Systems Engineer

Innovative non-GPS navigation system (AF083-165-SBIR):

Played a pivotal role in R&D of a terrestrial navigation technology using WCDMA, CDMA2000, GSM and HDTV. This

dual-SDR prototype is based on Time Difference of Arrival (TDOA) estimation with positioning accuracies of 10m and

above. Co-authored a technical paper published in the Institute of Navigation (ION)–ITM 2012.

Comprehensive system design; Successful development of baseband processors for GPS & cellular signals in

MATLAB

Involved in C/C++ signal processing and driver development working with open source GNURadio, UHD drivers.

Aided in development of Graphical User Interface (GUI) for prototype using Python-QT, GTK libraries.

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HARISH S SRIDHARA

High Efficiency WCDMA Power Amplifier for MUOS Handheld Radio (N092-159-SBIR):

Responsible for development of test framework for a Class-E power amplifier using Xilinx Virtex-6 ML605 hardware

platform.

Development of FPGA design with Microblaze processor and AXI eco-system in Xilinx Embedded Development

Kit (EDK).

Successful VHDL development of custom peripheral core for interfacing and control of FMC150 (A/D and D/A

convertors) to Microblaze processor in Xilinx ISE.

Development of C++ software for Microblaze for WCDMA signal and envelope generation.

Reconfigurable Low Power Mobile SDR for GNSS Integrity (AF121-156-SBIR):

Hardware architectural design of a low power SDR platform for processing of GNSS signals. In transition for further

funding, this technology is based on accelerated parallel computation schemes.

Successful development of GPS signal processing including Acquisition, Code and Carrier Tracking functionalities

etc. in MATLAB.

System and hardware architectural layout for the innovative SDR platform using Xilinx Zynq FPGAs and PCIe

interconnect technology.

Manipal Dot Net, Manipal, Karnataka, India

Digital design engineering intern – Embedded Systems 05/2006- 12/2006

Memory controller design: Headed the design team for successful development of flash memory controllers for very high

throughput and CPU load reduction. Responsibilities included VHDL development for implementing and simulating

controllers for NAND Flash, CompactFlash, PWM and Stepper Motor, SMbus for Altera Max II CPLDs.

Engineering intern – Image processing 01/2007- 05/2007

Successfully implemented JPEG encoding algorithm on embedded C programmable Stretch 6000 series of DSP processors

known for their FPGA based accelerated computation.

Bharat Sanchar Nigam Ltd, Kurnool, Andhra Pradesh, India

Telecommunications Engineering Intern

Underwent field study on the working of E-10B, OCB and EWSD (TAX) Exchanges and the outdoor cable plant network.

A CADEMIC P ROJECTS

Channel modeling of 60 GHz indoor wireless channel: As part of Wireless Devices and Systems (WiDeS) group at USC,

carried out channel modeling of 60GHz frequency using MATLAB simulations of the models proposed by the IEEE

802.15 3c and 802.11ad groups, Eigen Value Distributions (EVD) of the channel at different tones and the capacities of

MIMO systems.

Design of CMOS high frequency, broadband Low Noise Amplifier (LNA) as part of RF design course.

Design of low power rail-to-rail high bandwidth folded cascode CMOS operational amplifier. Project also included the

design of various configurations such as Operational Transconductance Amplifier(OTA), Self-biased Cascode.

P UBLICATIONS

M. Enright, H. Sridhara, “Advanced GNSS Integrity Using Signals of Opportunity”, ION ITM 2012.

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