Engineer Design
Resume:
JANET N. NGUYEN
Austin, TX 78750
Mobile: 512-***-****
Email: **************@*****.***
CAREER SUMMARY
. Over seven years of experience in
verification/validation/characterization and software design and
development using C, C++ and Perl.
. Five years of hardware design experience involving designing parts of CPU
and caches.
. Particular expertise in test case generation, formal verification,
simulation, coverage.
. Result-oriented problem-solver who learns new processes quickly and
develops strong working relationships.
TECHNICAL SKILLS
Programming Language: C, C++, Perl, Verilog, VHDL, Specman E, LabView
Logic/Circuit Design: Verilog, CMOS, Synopsys, Cadence
Operating Systems: UNIX, AIX, OS2, MS Window, DOS, MVS, VM/CMS
Hardware Architecture: PowerPC, x86, IA32, S/390, RISC/6000
PROFESSIONAL EXPERIENCE
Flextronics, Austin, Texas 2013 - present
Design Verification Engineer
o Work in the next generation of PC development team, responsible for test
development, execution and debug to ensure new system working as
expected.
o Trouble shooting failed test units down to the board and component
levels.
Responsible for solving customer issues by analyzing, debugging and provide
solution to the customer.
Manage deliverables and work with cross-functional teams to support product
requirements.
Write lua scripts to automate the testing.
IBM Corporation, Austin, Texas 2011 - 2013
I/O Development Engineer
o Worked in the System p Power I/O development team, responsible for test
plan development, execution and debug to ensure new adapters working as
expected.
o Translated hardware specifications into test units that will be used in
initial bring up, diagnostic, hardware system test and manufacturing.
Worked in Level 3 Product Engineer team, responsible for solving customer
issues by analyzing the provided snap data and provide
solution to the customer.
Wrote script to automate the testing.
o Set up a Unix/Linux based system to run tests.
AMD Corporation, Austin, Texas
2009-2011
Memory Validation/Characterization Engineer / Team Lead
Responsible for device, CPU and memory testing on multiple boards designed
for mobile, desktop and server environments.
Analyze the margining result variations and trends between boards, DIMMs
and CPUs to ensure the new designs meet or exceed the
margining requirements.
Support for HyperTransport (HT1 & HT3) Characterization, Compliance, OEM,
Design Qualification, PPCD and Oven Validation using
Automated Characterization Environment (ACE) and HDT
applications.
Programming in the ACE scripting language for DDR margining automation
along with Perl scripting.
Assemble platforms and various computer systems with devices such as purple
possum, rubato and HDT hardware.
Competent testing with K8Pat, SST, RSTPro and MarginStress programs.
Allegro viewer proficiency for signal and electronic component discovery.
Performed validation of the chip using Logic Analyzers, Oscilloscopes,
accomplished the task of finding bugs in the silicon and
test environment.
Bring-up validation data collection analysis, presented test strategy and
results to upper level management and customers
Intel Corporation, Austin, Texas 2006 - 2009
Low Power IA Silicon Validation Engineer
o Worked as a CPU post-Si validation engineer in Low Power IA group.
Responsible for creating execution qualification plan using random test,
executing the qualification plan, making sure to meet or exceed the
schedule.
o Performed silicon-level validation of silicon to ensure that the design
meets all functional product definition, develop/improve silicon
validation plans, debug and analyze silicon designs and issues related
to silicon. Analyzed and documented validation results, participated in
silicon design and validation design review meetings and provide failure
analysis support.
o Debug logic failures using internal debug tool called ITP and TLA.
Worked closely with design team to debug failures by analyzing the FSB
trace as well as using the hardware debug tool called ITP.
o Used internal tool called PSMI to inject sync points and capture a
trace that can replay and converge on the emulation model for
debugging.
o Responsible for installation and maintenance of the automation
environment which is used for job distribution, resource management,
statistic tracking as well as automatically doing the failure
minimization.
IBM Corporation, Austin, Texas 2004 - 2006
PowerPC Validation/Characterization Engineer
Responsible for determination and establishment of focused and random
validation methodologies and test plan development, test
writing and debug, tracking and resolution of design bugs.
Analyzing coverage holes and defining test strategy execution.
Performed validation of the chip using Logic Analyzers, Oscilloscopes,
accomplished the task of finding bugs in the silicon and
test environment.
Bring-up validation data collection analysis, presented test strategy and
results to upper level management and customers
System level board debug, isolate chip failures to key design area of the
chip.
Insure logic and circuit test coverage is sufficient.
Implemented Perl scripts to help automate the testing process.
MOTOROLA, Inc., Semiconductor Products Sector, Austin, Texas 1995 - 2002
Design Verification/Software Engineer
o Analyzed, designed, implemented, tested and released software for the
Verification Test Generator (VTG), which is used to generate and execute
millions of instructions to run and verify against the hardware model.
This tool offers different biasing techniques to generate interesting
test cases as well as requested test sequences.
o Designed, tested, and implemented enhancements to Motorola's MET logic
equivalence checking tool, which is based on both BDDs and ATPG
techniques. This tool is used to verify the functional equivalence
between two hardware designs, and if there is any discrepancy, it creates
the failed vectors, error candidates, and the schematic to help in
debugging the differences. This equivalence checking methodology
provided 100% coverage and significantly reduced time to market by
replacing simulation at subsequent phases of the design process. The tool
is used with white and black box testing methodologies.
o Designed, implemented, tested the simulation coverage tool which will
monitor the VCS
o simulator state machine and/or line coverage.
o Developed the Graphical User Interface for Motorola MJTAG tool which
implemented IEEE Std. 1149 for boundary-scan testing. The tool is
comprised of Test Program Generation, Test Program Execution, coverage
report and diagnose capability.
o Documented software designs, user manuals, and release processes on all
projects.
IBM Corporation, Poughkeepsie, New York 1990 - 1995
Software Engineer
o Designed, implemented, and tested embedded real-time LAN Emulation ATM
open system adapter for S/390 IBM mainframe computer on schedule.
o Integrated existing software modules and worked closely with hardware
engineers to debug software and hardware issues.
o Handled all aspects of software development from design, porting, and
debugging to delivery.
Hardware Design Engineer
o Developed logic designs for two chips that executed all scalar and vector
MPY instructions in both IEEE and Hex mode.
o Enhanced the existing 7 chips in L2 cache control area to support 10-way
coupling.
o Improved the chip timing by moving logic gates around storage elements,
by replacing logic gates, or by removing logic gates without changing the
functionality.
o Verified the functionality of the chip design by running random
simulations and hand-made C and REXX test cases.
o Participated in all phases of the chip design process including high
level design, behavioral generation, verification, logic synthesis, chip
testability, and timing analysis.
EDUCATION
Master of Science, Electrical Engineering
University of California, Irvine, California
Field of study: DSP and Communication
Bachelor of Science, Computer Engineering
University of Bridgeport, Bridgeport, Connecticut
Bachelor of Science, Electrical Engineering
University of Bridgeport, Bridgeport, Connecticut
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