Engineer Process
Resume:
TERESSA Lovette L. ANGLINMATUMONA
Fairfax, VA ***30
**********@*****.***
PROFESSIONAL
OBJECTIVE: A position in PROCESS DEVELOPMENT ENGINEERING, which will effectively utilize
extensive knowledge of Semiconductors, Oxide Etch Processes and Statistical Analysis in
an atmosphere conducive to professional growth and development; motivated by challenge and
diversity.
EDUCATION:
SAN JOSE STATE UNIVERSITY, San Jose, CA
M.S., Chemical Engineering Graduated: May 2005
* Worked Full-Time as Process Engineer Concentration: Semiconductors
Thesis Project: Characterization and Optimization of a New Gas Chemistry to Reduce ARDE
for High ASPECT Ratio Via Etch Process in a High Density ICP System
NORTH CAROLINA STATE UNIVERSITY, Raleigh, NC
B.S., Chemical Engineering and B.S., Applied Statistics Graduated: May 1999
AREAS OF
EXPERTISE: Background includes special classes and/or experience in:
Design of Experiments (DOE/ANOVA) JMP & Mintab Statistical Software
Statistical Process Control (SPC) SEM & Defect Analysis
Process Integration Requirements Vendor/Customer Relations
Departmental Liaisons Engineering Alliance
Guest Lecturer;: Design of Experiments (DOE) at SJSU
AFFILIATIONS: American Vacuum Society (AVS)
1) Poster Presentation at AVS 52nd International Symposium, Boston, MA, October (2005). Paper
Title: Characterization Methodologies for Unsaturated 1,3-C4F6 Plasma used to Investigate Aspect Ratio
Dependent Etch and Etch Characteristics with Comparison to Saturated c-C4F8. 2) Invited Talk at
NCCAVS PEUG User Groups, Sunnyvale, CA, May (2006) Subject: The Transition from Saturated (c-
C4F8) to Unsaturated (1,3-C4F6)Perfluorocarbons: Effects on Selectivity and ARDE in Via-hole Plasma
Etch Applications. 3) Poster Presentation at AVS 53rd International Symposium, San Francisco, CA,
October (2006). Paper Title: Plasma Chemistries for High-Aspect-Ratio Dielectric Etching Beyond 65
nm Node.
Job duties include:
ᴥCross-training and process development for dielectric etch of all TEL Unity; TEL DRM;TEL SCCM; and AMAT
plasma etch equipment platforms for Logic; NOR; NAND; and DRAM technologies.
ᴥProvided relevant support to internal and external customer relations for coordination of new equipment qualifications
and process certifications for dielectric etch applications.
ᴥDeveloped and characterized processes compatible with advance plasma etch techniques for dielectric technical platforms.
ᴥAble to provide knowledge of dielectric plasma etch techniques and effective troubleshooting skills to solve process problems.
ᴥExperienced with new plasma chemistry and equipment selections; including qualification; installation; and transfer.
ᴥExperienced process ownership includes STI Nitride; Self-Aligning-Contact; Spacer,Via (Dual Damascene);
& Poly-Hardmask Plasma Etch Applications.
CAN-AM Consultants, 10/03/2011-12/08/2011
Process Characterization Engineer
ᴥOwn PVD Process Characterization and Optimization for W/WN-W/ALSI/ITO Metal Film layers.
ᴥConducted PVD chamber characterization as a function of gas flows, chamber temp, DC power and gap position to
investigate the impact on uniformity, resistivity, film thickness and CALFACTOR.
ᴥResponsible for Ion-Implant low and high dose energy applications using a medium and high density implanter.
ᴥDesign and conduct design-of-experiments (DOE) and provide recommendation for process improvements.
Nuvotronics, LLC, Blacksburg VA (Start-up Company 6/2008 to 1/2009)
Sr. Process Development Engineer (MEMs Product Development), Tenure: 12/2/2008 to 1/8/2009
ᴥWorked with Product Lines to understand their specific product roadmap requirements and use as input for MEM
Platform road-mapping.
ᴥDeveloped & Implemented Statistical Process Control Database Systems across all fab modules.
ᴥTeam player with a strong sense of urgency to meet product requirements on schedule.
TERESSA Lovette L. ANGLINMATUMONA Page 2
Micron Technology, Manassas, VA; Contributions;: Process Owner for all TEL© DRMDielectric Etch Applications.
Process Module Owner (Dielectric Etch Applications), Tenure: 8/2006 to 2/2008
ᴥLed and developed process characterization experiments for low-k self-aligning-contact (SAC) for DRAM 45 nm node.
ᴥDesigned, conducted, executed and analyzed experiments such as response surface, screening, and split plots;
influencing the selection of plasma chemistry.
ᴥConducted SWR experiments to investigate causes of process variation and developed new processes to increase
product yield and improve process margin for wafer fabrication.
ᴥProvided close collaboration through net-meetings with engineers in Singapore in effort to develop & characterize new
SAC dry etch applications.
ᴥLed and coordinated new tool install qualifications, NPI, and product qualification and release for fab ramp and continuous
improvements; and interacted productively with a diverse team sharing these goals.
Intel Corporation, Rio Rancho, NM & Santa Clara, CA
Co-Develop/Process Transfer Engineer, Tenure: 3/2004 to 8/2006
ᴥLed, developed, conducted SWR experiments for the new descum step for a 30% improvement to inline defects for 32
nm node flash memory dielectric application.
ᴥSupported Quality, Reliability and Integration Teams to ensure that technology meet the quality and reliability specifications.
ᴥDry Etch Team Leader for tool downs and fab excursion/SWATS impacting yield performance.
ᴥImproved Tool Uptime by 34% by resolving etch rate fallout and particle issues.
ᴥEvaluated tool capability, tool mismatches relative to the golden tool; & process performance for different plasma etcher
platforms; based on inline metrics & end-of-the-line parametric data.
ᴥPerformed process characterization & tool matching for new and existing plasma etch processes.
ᴥTransferred processes from R&D to HVM production; including recipe development and modification.
ᴥEstablished new procedures and qualification plans for new product introduction (NPI).
ᴥInvestigated, established and implemented requirements for equipment, tooling, materials and methods of production
leading to minimized cost, enhanced quality, and increased throughput.
Advance Micro Devices (Submicron Development Center), Sunnyvale, CA
Process Engineer, Tenure: 5/1999 to 4/2003
ᴥInvestigated and developed new plasma chemistry for high-aspect-ratio devices for 130 nm node technology that led
to a 2 to 1 improvement in selectivity; ARDE & dimensional control.
ᴥManaged time-line and cost in reducing particles in only two months; Total cost to restore solvent tool at .15 um
detection level using SP1 was $4,500 with a savings of $10K.
ᴥOptimized wet clean process for BEOL resulting in a 48% yield increase for 4 Mb and 29.2% for 1 Mb.
Developed:
ᴥDeveloped AMD 1st-ever Bare Wafer Inspection Methodology Using Orbot Coordinates. New
methodology enabled cheaper; and faster studies of defects.
ᴥDeveloped FSI Temperature methodologies to test cleaning efficiency using APM chemistry.
New methodology led to improved cleaning efficiency using APM chemistry. Developed cleaning
efficiency methodology for FSI system.
ᴥDeveloped 1st contact clean process; recipe was considered for a standard across all AMD fabs.
FUJITSU Network Communications, INC., Raleigh, NC
Quality Assurance Intern, Tenure: 5/1998 to 1/1999
ᴥ Utilized SAS programming for bandwidth communication products to develop
regression model and statistical templates to perform descriptive statistics on software code
parameters; instrumental in ISO 9000 audit.
DUPONT Chemicals Company, Wilmington, DE
Process Development CO-OP, Tenure: 12/1992 to 12/1993
ᴥPerformed experiments on a laboratory scale “Breadboard Refrigeration System” to
quantify refrigerant characteristics; subsequently co-authored technical paper on the
subject. Supervised technician and trained team members.
XEROX Corporation, Webster, NY
Process Development Intern, Tenure: Summer, 1989-1992
ᴥConducted pilot scale studies for toner extrusion processes.
ᴥDeveloped operating procedures for new dryer process and trained technicians.
REFERENCES: Excellent Professional and Personal References Available Upon Request.
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