Management System
Resume:
SAMARENDRA KISHORE
PROFESSIONAL EXPERIENCE:
13+ years of industry experience in:
ASIC Design Cycle of ASIC Core Design-Verification & Simulation
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RTL Functional Verification using HVL - ‘e’ Language, System Verilog, Vera and
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C language
ERM, VMM and RVM based Verification development
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Technologies including Ethernet, Ethernet Switch, AHB, AMBA,
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HDLC, SONET/SDH, GFP, LAPS, SPI-3, FC and IEEE- 1394.
PROFESSIONAL SKILLS:
Hardware Description Language: Verilog HDL, VHDL
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Hardware Verification Languages: ‘e’ Language, System Verilog and Vera
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EDA Expertise: Behavioral/RTL modeling, IP Core logic verification
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EDA Tools: NC Simulator, Verilog-XL, ModelSim, Debussy, VCS
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Hardware Architectures: 8085
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Programming Languages: C/C++, 8085 Assembly Language
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Operating Systems: Unix(Solaris), Linux, Windows
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Scripting Languages: Perl, tcl, Bash Shell
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Hardware Modeling: System Verilog
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EXPERIENCE DETAILS:
Qualcomm Canada, Toronto – July 2006 till date
Role: At present, managing a team and providing technical, functional and
process based expertise to the team. Leading a small cross functional
team to develop IP based build flow for the entire verification group
located at Toronto. I am involved in verification planning and tracking of
Ethernet Subsystem and System Level test bench from architectural block
till coverage completion. I am also involved in supporting various scripts
for the build flow and job management. I am also involved in developing
Gate Level Simulation test benches as well as debugging them.
Achieved a 100% successful silicon tape out rate from past 7 projects. I
was involved in looking after Platform Management, Build Flow as well as
regression management. This role also had planning, delegating,
scheduling, tracking and implementation of the projects. It also involved
mentoring team members as and when they need it. Good in both Macro
and Micro level management. Developed a three tier process to track the
progress of verification team at different stages and if need arises it goes
up to daily status reporting too.
Technology Domain: Ethernet, Ethernet Switch, BIST and BootROM
Tools: VCS, Perforce
Languages: System Verilog, Shell (bash), Perl, Tcl and Verilog
Platform: Linux
Infineon Technologies – November 2003 to June 2006
Role: Worked in various roles as team lead and individual contributor. My
scope of Job is to plan, schedule and implement coverage plan as well as
verification plan for the team. This role involves mentoring other team
members and provides technical guidance to them.
Responsible for the implementation of Test plan, Creating Corner Cases,
develop verification environment of various blocks, subsystem level Test
Bench and system level test benches.
Technology Domain: CCAM, Leaky Bucket Shaper, HDLC
Tools: ModelSim, Debussy, Specman Elite
Languages: ‘e’ and VHDL
Platform: Solaris
Einfochips, India – Dec’2000 to Oct’2003
Role: Worked as Individual contributor. I was involved in planning and
architecture of various block level Test benches. Some of my expertise
were in architect and develop test bench which can be used by designers.
Also developed a perl script of generate XML files, which suites internal
tools of the team. Some of the efforts were also onsite. Prepared Test
scenarios & running regressions which contributed towards achieving 99%
functional coverage. Involved in identifying corners cases creating new
tests to cover those scenarios and achieve more than 90% of coverage
based on block to block level analysis with designers and design
managers.
Implement and maintain regression script
Technology Domain: SPI3, Sonet, GFP, LAPS
Tools: ModelSim, NC Verilog, Specman Elite
Languages: ‘e’, C, VHDL, Perl
Platform: Solaris 5.8, Unix
EDUCATION QUALIFICATION:
• Degree: Bachelor of Engineering (B.E)
• Year: 1995-1999
• University: Karnataka University
REFERENCES
On Demand
ADDRESS OF CORRESPONDENCE:
Samarendra Kishore
183 Hammersly Blvd
Markham, ON
Contact no. 647-***-****
E-Mail : - acbax9@r.postjobfree.com
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