Design Engineering

karthik kothandaraman

Graduate student at The University of Texas at Dallas, actively seeking Spring/Summer 2014

internship

************@*****.***

Summary

Seeking a internship position starting January 2014 in a leading semiconductor Industry in the field of Digital

Design/Verification or Testing.

SKILLS :

# CAD Tools:

Cadence: virtuoso & composer-schematic, Encounter

Synopsys: Design Vision, VCS, Liberty NCX library characterization tool, Prime Time

Other tools: Xilinx ISE; Modelsim; Hspice; Teramax ;Altera-Quartus; OrCAD; TI code composer Studio.

# Signal processing : MATLAB, LabVIEW, AWR Microwave office

# Scripting Language : Perl

# Programming Languages : C, Embedded C, C++, Java

# Hardware description Languages: Verilog, VHDL

# Operating Systems : Windows, Unix.

# Miro-controllers: ARM Cortex M3, MSP 430

Experience

Student worker at University of Texas at Dallas

August 2013 - Present (4 months)

RF Engineer Intern at GTL USA Inc.

June 2013 - August 2013 (3 months)

# Worked for Ericsson in the field of network optimization and cell planning and Performed Field Testing in

AT &T LTE and UMTS sites. Used Ascom-TEMS Investigation tool to analyze TCP and UDP

downlink/uplink throughput, Inter/Intra handover, Inter Frequency Handover and IRAT handovers.

# Performed verification and validation of LTE devices by analyzing the KPI parameters. Designed various

scripts in TEMS to automate the testing process which tests the CSFB call quality, network bandwidth, ping

latency and Jitter. These scripts are used for performing single site verification and cluster drives. Analysis of

network performance through Iperf and wireshark logs

# Coordinated and carried out a LTE field testing project for Copper Valley Telecom in Alaska.

# Dealt with post processing of log files, Prepared Reports and presentations on test results for pre-launch

optimization.

CPLD Design Developer Intern at Benchmark Electronic Systems

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June 2012 - July 2012 (2 months)

# Designed applications in Altera MAX V CPLD using Quartus II software. Modelsim was used for

simulation and design verification.

# Developed LabVIEW interface for digital Communication Trainers

1 recommendation available upon request

Junior Analyst at Temenos

July 2011 - June 2012 (1 year)

# Worked with Product Analysis and Customer Support Team. Dealt with T24- Arrangement Architecture

software Module, bug analysis, product enhancements and development for worldwide banks.

# Used Perl scripting to automate testing and software maintenance.

1 recommendation available upon request

Education

The University of Texas at Dallas

Master of Science (MS), Electrical Engineering - Digital Systems, 2012 - 2014

Anna University

Bachelor of Engineering (B.E.), Electrical and Electronics Engineering, 2007 - 2011

Activities and Societies: Member of student organizing committee for International Conference on Biomedical

Instrumentation and Health Care (ICOBIAHC)

Projects

Standard Cell library Design and implementation of Shortest Path Algorithm

August 2012 to Present

Members:karthik kothandaraman

A Digital System was designed in Verilog to find shortest distance between the given set of coordinates.

Design, layout and cell library generation was done for the cells (NAND, NOR, NOT, XOR, OA221, MUX,

and D-Flipflop). Simulated waveforms and measured the Performance of the above cells in Hspice.

Placement and routing of the design was done using Cadence Encounter.

Design of 1 k-bit SRAM Memory using IBM 130 nm Process

June 2013 to Present

Members:karthik kothandaraman

The SRAM was designed using Cadence Virtuoso Layout editor. The Associated circuits like Decoders,

Precharge and Sense amplifier was manually sized and designed. All the individual gates were routed

manually and verified for DRC and LVS errors. The worst case read and write time were calculated by

Hspice. The waveforms were verified in Synopsys Waveview.

Implementation of KL Algorithm for Partitioning IBM standard Digital Circuits

August 2013 to Present

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Members:karthik kothandaraman

Developed and optimized a program to implement KL Algorithm, where complex data structures were

formed from IBM Benchmark Netlist files and manipulated. The first step was to perform the initial cut and

bipartition the circuit with approximately equal areas. The main concern was to reduce the cut size from the

initial cut to final cut without compromising on the area criteria on both partitions.

Design and Verification of a 32 Bit ALU

January 2013 to Present

Members:karthik kothandaraman

Developed specifications and designed the architecture for a 32 Bit ALU following the ASIC design flow. A

finite state machine was designed to accept the patterns given and carry out corresponding arithmetic

operations. Implemented RTL logic in VHDL and synthesized it using Design Compiler. Physical

Verification was conducted and the spice netlist was extracted. Setup and Hold violations were fixed by static

timing analysis using Primetime.

Fault Analysis and Testing of digital systems

January 2013 to Present

Members:karthik kothandaraman

All stuck-at faults and test vectors are found for the given circuit .Test patterns were generated and fault

coverage was determined for ISCAS89 s27 benchmark using Teramax (ATPG). Also, the area and delay was

determined before and after automated scan chain insertion.

Optimization of Cache and Branch Predictor in Alpha 21264 microprocessor

February 2013 to Present

Members:karthik kothandaraman, Somesharun Vijayadurai Nirmala, Rokesh Jayasundar

Design choices such as # of levels, size, Associativity, replacement policy were analyzed to come up with an

optimal cache configuration. Different branch predictor configurations were simulated. The

performance of predictors (two level, combining and Bimodal) was compared using 3 different benchmarks.

Perl scripting was used extensively along with Simple Scalar tool to carry out the simulation and extracting

the relevant data.

Design of a Differential amplifier : Analog Integrated Circuit Design

August 2012 to Present

Members:karthik kothandaraman

A two-stage differential input and single ended output amplifier was designed using TSMC CMOS 0.35 µm

technology for a set of specifications, [Phase Margin> 60 , Power<1mW, Differential Voltage gain>60dB,

Unity gain B.W>25MHz, Slew rate>10V/µs, Rin>10M#]. Transient, AC/DC analysis, CMRR, Phase margin,

output voltage swing range and power dissipation graphs are plotted using Cadence Analog Circuit Design

Environment.

Traffic control system integrated with GPS – RF and Microwave Systems Engineering

August 2012 to Present

Members:karthik kothandaraman

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RF system was designed for the detecting the speed of moving traffic using radar and suggesting an

alternate route to the driver with the use of on board GPS system. The proposed system takes into account

the real-time traffic densities in the course of the journey and automatically re-routes the path to destination

so as to avoid unexpected delay. a K-band Doppler-Radar transceiver is used to determine speed and a 5.5

GHz LEO satellite link is used for communicating the traffic information to vehicles. The Overall system

Gain, cascaded P1dB and cascaded Noise figure is determined using AWR system level implementation.

Yield analysis and worst case analysis is also simulated

Design of a two stage broadband RF amplifier as a front-end amplifier for optical receivers

January 2013 to Present

Members:karthik kothandaraman, Nisha Nandakumar

Designed and analyzed the input and output stage stability of a broadband amplifier, its matching conditions

and Transimpedance gain over a frequency range of 0.1 to 12 GHz. Stability Analysis, A.C and D.C.

Analysis, plot of input and output stability circles, output impedance and K-Delta test were carried out using

AWR

Courses

Bachelor of Engineering (B.E.), Electrical and

Electronics Engineering

Anna University

Digital Logical Circuits

Linear Integrated Circuits

Communication Engineering

VLSI

Master of Science (MS), Electrical Engineering -

Digital Systems

The University of Texas at Dallas

VLSI Design Fall '12

Analog Integrated Circuit Design Fall '12

RF and Microwave systems engineering Fall '12

Computer Architechure Spring '13

Advanced Digital Logic Spring '13

RF and Microwave Amplifier Circuits Spring '13

Microprocessor Systems Lab Fall' 13

Design and Automation of VLSI systems Fall' 13

Algorithmic Aspects of Telecommunication Networks Fall' 13

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Skills & Expertise

C++

Verilog

Synopsys tools

Cadence Virtuoso

Xilinx ISE

Altera Quartus

SPICE

ModelSim

VLSI CAD

Orcad

NI LabVIEW

AutoCAD

Microsoft Office

Perl

AWR Microwave Office

Ascom-TEMS Investigation

LTE

RF

VHDL

CPLD

Wireless

Matlab

Testing

Labview

Integrated Circuit Design

Unix

TI Code Composer

Embedded C

ARM Cortex-M3

MSP430

Physical Design Automation

Signal Processing

Java

Wireshark

Certifications

Master Diploma in Electronic Design and Automation

CADD CENTRE March 2010

Temenos Certified Consultant

Temenos December 2011 to September 2013

Volunteer Experience

coordinator at University of Madras

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Took part in mega tree plantation event, book collection campaign and Global Warming Rally conducted by

the University of Madras under its national service scheme.

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karthik kothandaraman

Graduate student at The University of Texas at Dallas, actively seeking Spring/Summer 2014

internship

************@*****.***

2 people have recommended karthik

"Karthik's technical knowledge on the areas of CPLD design and digital communication concept

implementation in LABVIEW worked was highly commendable. He is a self-motivated, self-learning, duty

bound and committed person. He can work independently and has the enthusiasm to complete the work on

time. He is also very sincere, friendly and hardworking. His documentation skill is exemplary. I am sure that

he will be an asset to any organization"

Kamala Kris, was karthik's client

"Karthik has worked with T24 product for close to 11 months. He was a fast learner and worked hard towards

meeting his deliverables. He played his role independently and was commited to his work. Good attitude and

a good team player."

Thiripurasundari ilamadi, Senior Manager, Temenos, managed karthik indirectly at Temenos

Contact karthik on LinkedIn

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