Supply Chain Manager

PHILIP C. DAMBERG

***** ********** ***** *********, ** 95014

408-***-**** (cell)

***********@*****.***

OPERATIONS EXECUTIVE / MANUFACTURING, SUPPLY CHAIN, R&D

Strong Start-up and Ramp to HVM experience including high mix, custom products

Proven experience in new Product Development, Prototyping, Characterization and Qualification,

Yield Improvement, Cycle Time Reduction, Cost Reduction

Technical Expertise in IC Fab, Packaging and Connector Materials, Processes and Equipment

Over 20 years of experience in advanced IC packaging: CSP, MCM, PoP, Flip-Chip, W LP, TSV

Strong experience with Semiconductor and Electronics Supply Chains especially for IC

Packaging and Mobile (Smartphones, Tablets, Notebooks) - substrates, interposers, adhesives,

encapsulants, foundry, OSAT, EMS

Solid experience in Quality, Reliability, Failure Analysis and Continuous Improvement: TQM,

ISO9002, Six Sigma, Lean

Experience managing Offshore based teams in Asia - Supply Chain and R&D

IP Strategy – Licensing, Acquisition, Claim Charting

Experienced in new product Market Research and Competitive Analysis

Frequently work with Sales to provide technical presentations directly to customers

Authored or co-authored 12 US patents and 16 patent applications pending

Presenter at a number of technical symposium/conferences and panel sessions, co-authored

numerous technical papers and trade magazine articles

PROFESSIONAL EXPERIENCE

2012 – 2013

NEOCONIX INC., Sunnyvale, CA

Neoconix designs and manufactures miniaturized, high-performance electrical connectors for mobile,

enterprise IT and industrial markets (start-up company, 35 employees when hired)

Vice President of Operations

Responsible for worldwide operations including: a domestic facility for high margin telecom

products and new product development; and a supply chain and engineering team at our high

volume manufacturing partner in China

Successfully ramped first mobile product to meet an aggressive supply schedule for a Tier 1

customer notebook computer

Developed new flows to increase mobile product yields by 20%

Densified materials layouts to reduce mobile product costs by over 50%

Established the supply chain for our new compressible coverlay technology for a major new

mobile gaming product and provided technology transfer for a successful product ramp

Departed Neoconix as part of a 65% reduction in force down to 8 employees May 2013 due to

reduced demand and low funds

1997 – 2012

TESSERA, INC. / INVENSAS CORPORATION, San Jose, CA

Tessera develops, invests in, licenses and delivers innovative miniaturization technologies and products

for next-generation electronic devices ($200M in annual revenue; 1,000 employees)

Vice President of Product Engineering 2010 – 2012

Responsible for 4 departments including a Supply Chain team in Japan, providing physical

modeling, design, materials development, process development, assembly, test, reliability

stressing, failure analysis and operations support for R&D, IP acquisition and licensing programs

Process/product development for xFD DRAM memory product platform now used in

ASUSTeK Ultrabook computers, Dell notebooks and Intel Xeon-based servers

Process/product development for the new BVA product family recently awarded the Frost &

Sullivan 2013 North American Customer Value Enhancement Award

Installed Cu wire bonding, micro-ball flip chip and underfill, film assist and compression

molding process capabilities for BVA development to assure low risk and low cost adoption

for advanced computing and mobile packaging customers

Upgraded analytical capabilities (2D and 3D x-ray, acoustic scanning, Moire, FTIR, TMA,

DMA, profilometry, micro-indent, FIB cross section, DRIE, FE SEM and EDX) for improved

resolution for IP development and IP licensing and acquisition decision making, helping

secure a number of new license agreements

Helped disposition more than $10M/year in IP transactions as a member of the patent review

teams for IP purchase, sale and licensing

Contributed more than 10 patents applications per year as a member of the patent application

preparation team

Controlled spending to within 10% of budget

Vice President of Advanced Packaging 2005 – 2010

Responsible for development of fine pitch interconnect technologies and intellectual property

Package development, prototype assembly, reliability, advanced technology R&D teams

Substrate R&D team in Japan

Significant expansion and strengthening of semiconductor packaging IP portfolio

µPILR Fine Pitch Package-on-Package (PoP) and µPILR Cu Pillar Flip Chip

Wafer Level Packaging (WLP) and W afer Level Memory Stacking

Embedded active and passive devices

Impedance controlled, high performance DRAM stacking

Silent Air Cooling (SAC) - Corona based cooling

Senior Director, Package Engineering and Prototype Manufacturing 2000 – 2005

Responsible for package development, prototype assembly, reliability, manufacturing and

program management for internal, commercial and government sponsored advanced electronics

miniaturization projects

Authored proposals and secured numerous contracts

Programs managed to meet milestones and complete deliverables on schedule contributing

to revenue growth allowing IPO in 2003

Significant contribution to IP portfolio: Folded stacked memory using flex substrates; FPGA,

microprocessor and stacked memory signal processing modules; Miniature wireless recorders

and wireless sensors; Dense MRAM stacking

Developed solder ball stacked memory – foundational to Package-on-Package (PoP) widely

used in today’s smartphones and tablets

CSP Technology Transfers to U of Alaska at Fairbanks, ND State U, MISCIR (Morocco)

Director, Manufacturing and Product Engineering 1997 – 2000

Responsible for package development, prototyping, manufacturing, reliability and technology

transfer for the Tessera µBGA Chip Scale Package (CSP)

Successfully ramped volume from sampling to 250,000/month to meet demand

Installed quality systems for successful ISO9001 certification

Selected and installed shop floor control and ERP systems

Improved assembly yields to 99%+

Developed and provided Technology Transfer to Licensees in Taiwan, Japan and Italy

Developed the μBGA DRAM package technology still broadly used today

1983 – 1997

LSI LOGIC CORPORATION, Cupertino, CA

LSI designs semiconductors and software that accelerate storage and networking in datacenters, mobile

networks and client computing ($2.4B in annual revenue; 5,300 employees)

Wafer Fab Operations Manager 1994 – 1997

Responsible for providing metallization layers for CMOS gate array and standard cell products at a

capacity of 2,500 wafers per week

240 personnel in 8 departments

Maintained world class cycle times with high product mix

Managed $33M facility upgrade for advanced metal deposition processing

.

Packaging Assembly Operations Manager 1983 – 1994

Responsible for package assembly for advanced ASIC devices

280 personnel in 6 departments.

Managed all aspects of the start-up of a fully automated packaging assembly line including

hiring all staff, designing process flows, workspace and equipment layout, contracting

construction of facilities, purchasing equipment and developing training

Installed TQM to achieve and sustain ISO9001 certification

Sustained world class cycle times (3X theoretical) by installing short cycle tools, pull methods

Formed relationships and provided technology transfer to OSATs for mature products.

PRIOR ENGINEERING & ENGINEERING MANAGEMENT POSITIONS

Sustaining and development engineering for packaging commercial and military ICs

Experience working off-shore: Thailand, Korea, Philippines

Developed and introduced interdigitated leadframe and plate molding processes

Yield improvement

U.S. AIR FORCE

Pilot, rank of Captain

EDUCATION

BS, Engineering Management, U.S. Air Force Academy

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