Design Engineer

CURRICULUM VITAE

Kumar Jyoti Narayan

Email:*.*.***********@*****.***

Mobile:+91-903*******

+91-923*******(alternative)

Bangalore

Entry level positions as Design/Verification Engineer preferably in ASIC domain.

OVERVIEW

• Good understanding in Digital logic design& Electronics fundamentals

• Good understanding of the ASIC/FPGA design flow

• Experience in Verilog HDL to write synthesizable RTL, self-checking test benches&

Test benches in System Verilog

• Very good knowledge on Verification methodologies(UVM)

• Experience in using industry standard EDA tools for the Front-end Design and Verification

PROFESSIONAL QUALIFICATIONS

Maven Silicon Certified Advanced VLSI Design and Verification course

From Maven Silicon VLSI Design and Training Center, Bangalore

Year : July 2013-December 2013

ACEDEMIC QUALIFICATIONS

Bachelor of Technology in Electronics and Communication

Biju Patnaik University of Technology, Odisha

Aggregate : 67.50%

Diploma in Electronics and Communication

State Council of Technical Education & Vocational Training,Odisha

Percentage : 69.66 %

Secondary Education

Board of Secondary Education,Odisha

Percentage : 65.87 %

TOOLS&TECHNICAL SKILLS

HDLs : Verilog

HVL : System Verilog, PSL

Verification

Methodologies : Coverage Driven Verification, Assertion Based Verification

TB Methodology: UVM

EDA Tools : Modelsim and Xilinx-ISE

Domain : ASIC/FPGA Design Flow, Digital Design methodologies

Knowledge : RTL Coding, FSM based design, Simulation, Code Coverage,

Functional Coverage, Synthesis, Static Timing Analysis, ABV

Programming

Languages : OOPs, (C, Assembly Language in 8085 )

Tool/Softwares : Circuit maker, MATLAB,Pspice

Operating systems: Windows & Ubuntu

VLSI PROJECTS

Basic AMBA Advanced Extensible Interface (AXI4) Protocol Verification (Currently

Working)

HVL: System Verilog

Methodology: UVM (Universal Verification Methodology)

EDA Tools: Questa – Verification Platform and ISE

Description: The AMBA AXI protocol is targeted at high-performance, high-frequency

system designs and includes a number of features that make it suitable for a high-speed

submicron interconnects. The AXI protocol includes optional extensions that cover

signalling for low-power operation.

Verified the protocol using Verilog HDL.

Architected the class based verification environment using system Verilog and

UVM methodology.

Generated functional and code coverage.

GPIO Core Verification

HVL :SystemVerilog

TB Methodology :UVM

EDA Tools :Modelsim, Questa-Verification Platform

Description :

Architected the class based verification environment using UVM

Verified the RTL module using SystemVerilog

Verification of the RTL module using UVM

Generated Functional coverage for the RTL verification

Router 1x3 – RTL design and verification

HDL : Verilog

HVL : SystemVerilog

TB Methodology : UVM

EDA Tools :Modelsim, Questa-Verification Platform and Xilinx-ISE

Description :

Architected the design and described the functionality using Verilog HDL.

Verified the RTL model using Verilog.

Generated Code coverage for the RTL verification sign-off Synthesized the design

Architecting the class based verification environment using UVM

Verification of the RTL module using UVM

Generation of functional coverage for the RTL verification

Dual Port RAM – RTL design and verification

HDL : Verilog

HVL :SystemVerilog

EDA Tools :Modelsim, Questa-Verification Platform and Xilinx-ISE

Description :

Implemented the Dual Port RAM using Verilog HDL independently

Verified the RTL module using Verilog& SystemVerilog

Architecting the class based verification environment using UVM

Verification of the RTL module using UVM

Generated Code coverage & Functional coverage for the RTL verification sign-off

Synthesized the design

ACEDEMIC PROJECTS

Speed control of DC motor using Microcontroller

Invertor

TRAINING AND INTERSHIPS

Pursued VLSI training from Central Toolroom & Training Centre Duration: 1 month

DECLARATION

I hereby declare that the information furnished above is true to the best of my knowledge.

Place: Bangalore Signature: Kumar Jyoti Narayan

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