Design Engineer Project
Resume:
RESUME
Masthan . K e-mail :
acb71t@r.postjobfree.com
Contact no. : +91-
CAREER OBJECTIVE
Dedicated professional seeking suitable position that would enable me to broaden my
current skills and challenge my various abilities in ASIC Physical Design.
SUMMARY
Having 2+ years of technical experience with Intel Through Technosoft Development
India Pvt Ltd in ASIC Physical Design field.
Good in all aspects of ASIC Physical Design flow from Netlist to GDSII which includes
Floor planning, Placement, Clock tree synthesis, Routing, DFM, DRC and LVS.
Strong in Timing Analysis.
I have clear concepts of understanding, analyzing & fixing the timing violations.
Good knowledge in digital circuit design and Low power design.
Good in Crosstalk analysis & IR Drop analysis.
Good knowledge in CMOS circuit concepts.
I have good knowledge in Writing Hardware Description Languages such as VHDL and
Verilog.
TECHNICAL SKILLS
Strong in static Timing Analysis.
The concepts of understanding, analyzing & fixing the timing violations.
Good in Electrical circuit’s analysis, and Digital design concepts.
Good understanding of CMOS circuit concepts.
Languages : VHDL, Verilog, basic TCL and C.
Tools used : ICC, Pt, Star RCXT, PTSI, caliber and Xilinx.
Simulation : Modelsim, ISE Simulator, PSPICE.
Operating Systems : Windows, Linux.
WORK EXPERIANCE
PROJECT 1
Clint: Intel
Duration: 2012 to till date
Designation: Design Engineer I
Foundry: Intel 8LM
This project is targeted to 22nm @ 1GHz system clock. My Responsibilities include for
executing the complete physical design flow from Netlist to GDSII which includes Floor
Planning, Placement, Clock Tree Synthesis, Routing, Crosstalk Analysis, Parasitic Extraction,
DRC, LVS, IR Drop Analysis, Static Timing Analysis and ECO. Worked on many timing critical
and congestion blocks under tight schedule.
Tools used: ICC, SOC Encounter, Star RC extractor, Synopsys.
PROJECT 2
Clint: Intel
Duration: 2011 to 2012
Designation: Design Engineer I
Foundry: Intel 11LM
This project is targeted to 32nm @ 1GHz system clock. My responsibilities include
executing the block level P&R starting from floor plan to GDSII and delivering the timing closed
and DRC/LVS clean database to chip integration team for tapeout. Which includes Floor
Planning, Placement, Clock Tree Synthesis, Routing, Crosstalk Analysis, Parasitic Extraction,
DRC, LVS, IR Drop Analysis, Static Timing Analysis and ECO. This involves understanding the
basic data flow inside my block and communication between my block and remaining blocks at
chip level.
Tools used: ICC, SOC Encounter, Star RC extractor, Synopsys.
ACADEMIC QUALIFICATION
Bachelor of Technology in Electronics and Communication Engineering from JNTU
University in 2010.
PERSONAL DETAILS
Father Name : Mr. K. Chengalarayudu.
Mother Name : Mrs. Lakshmi.
Permanent Address : Yellayapalem, Kodavaluru (Md),Nellore(Dt),
Andhra Pradesh, Pin:-524366.
Date of birth : 09-06-1989.
Sex : Male
Phone Number : +91-988*******.
E-mail id : acb71t@r.postjobfree.com
Personal Interests : Reading books, Playing Cricket, cooking.
DECLARATION
I hear by declare that the above mention information is correct up to my knowledge and I
bear the responsibility for the correctness of the above mentioned particulars.
Date: Signature
Place: (Masthan K)
Contact this candidate