Engineer Manager

Joseph Ousley, Jr.

*** ******* ******, **********, ** 55082

Tel: 612-***-**** E-mail: acb4lg@r.postjobfree.com

Profile

Materials Engineer offering a broad technical background in problem solving, process development, and

project management. Expertise in electroplating, materials, electronics packaging, and failure analysis.

Professional Experience

NVE Corporation

Senior Process/Packaging Engineer 2001-Present

Developed plating process for NiFe alloy in a pattern on virtually all NVE wafer products.

•

Three versions of custom plating equipment were implemented during my term.

Packaging support for products packaged in India, Thailand, and Philippines, including

•

MSOPs, SOICs, TDFN, xDFN, and COB products. Included regular communications and

company visits, including process and quality audits, as well as on-the-floor process

improvements and designed experiments. For DOEs, I have used StatEase and JMP to design

the experiment and analyze the data.

Implemented a data acquisition system to measure temperature and ppm oxygen in a polymer

•

cure oven used daily in production. Records were retained and available for review online.

Safety Manager: initiated safety glasses program, Lock out/Tag out, spill control, respirators,

•

protective clothing, and written safety procedures.

Set up semi-automated wastewater treatment operation which included pH adjustment and

•

polishing for Ni metal. Defined a plan for completely automated operation with online Ni

measurement.

Environmental and workplace contact interface for regulatory issues which included safety

•

compliance, wastewater treatment/compliance, and materials safety/handling compliance.

Set up back grinding and dicing operation and introduced dice-before-grind and back grinding

•

down to 4 mils with existing equipment.

Implemented both wafer level and packaging process improvements to increase and stabilize

•

high voltage endurance of the isolator product line.

Primary interface for surface and failure analysis.

•

Science Incorporated, Minneapolis, MN

1998-2001

Senior Process Engineer

Directed development, testing, and realistic specifications for a biocompatible elastomer film.

•

Developed process for application, curing, and testing of a medical UV adhesive use din a

•

fluid path application.

Selected vendors, coordinated prototype efforts, and developed testing for 2-shot overmolding

•

of silicone and TPE on plastics.

Developed tests using LabView and other computer-based data acquisition of temperature,

•

position and pressure.

Developed CO2 cleaning process. Determined material requirements for bio-compatibility.

•

Implemented use of a high-resolution inspection camera.

Joseph Ousley, Jr.

Silicon Graphics, Inc. Chippewa Falls, WI

1996-1998

Program Manager for Advanced Packaging Development

• Managed financial, technical, and reporting for SGI’s participation in SHOCC (Seamless

High Off-Chip Connectivity), a DARPA-funded consortium.

• Spearheaded completion of SHOCC test vehicles by working closely with ECAD,

electrical, and fabrication technical people.

• Directed efforts to create film-based MCMs and printed circuit boards.

• Lead efforts to measure and present data on thin film stress and adhesion in experimental

polymers with copper metal.

Cray Research, Inc. Chippewa Falls, WI

1992-1996

Senior Materials Engineer

• Discovered the cause of and determined risk exposure for corrosion of copper and tin lead

frames exposure by iso-octyl thio glycolate- an additive in certain PVC/ABS polymers.

• Devised test plan for, conducted, and supervised extensive material compatibility testing.

• Conducted thermal tests on a new cost saving perfluorinated fluid.

• Developed analytical tests for reclaiming $350,000 of Fluorinert using computer acquired

spectroscopy data.

• Solved high I/O BGA/CGA soldering problems using designed experiments and analytical

tools.

• Published internally “Lessons Learned: A Guide for Problem Prevention in Design”.

• Created an internal searchable WWW page for materials compatibility data.

1988-1992

Failure Analysis/Materials Engineer

• Resolved $1M electrical ground drop problem by leading a redesign team.

• Introduced palladium-based contact metallurgy for solderable pin-style connectors.

• Used FTIR to discover antistat-induced softening of 22 layer FR-4 circuit boards.

• Introduced removable, dispensable, flexible epoxy thermal adhesive, solving a $100,000

repair problem and developed the companion repair procedure.

• Performed screening experiments to select optimum solder fluxes for large multilayer

circuit boards.

• Evaluated/introduced terpene-based Freon replacement cleaning solvent.

• Developed FTIR search library for identifying unknown in-house materials.

• Developed analytical technique to detect PFIB (a toxic gas) by gas chromatography.

1987-1988

Process Development Engineer, Cray 3 Development

• Developed backside/frontside spin-on polymer protection process for GaAs circuits.

• Developed mechanical/chemical grinding/polishing process for GaAs wafers.

• Developed process for megasonic cleaning/drying of GaAs wafers.

1986-1987

Process Development Engineer

Developed thick-build electroless copper process on polyimide.

•

Joseph Ousley, Jr.

Developed thin-film nichrome resistors anodized aluminum capacitors on polyimide.

•

Developed wet etching chemistry for palladium, chromium, nichrome and Si vias.

•

Sputtered palladium, chromium, titanium/tungsten, copper, and nichrome as initiation

•

and protective films for plating as well as for resistive and capacitive elements.

•

Micro Switch/Honeywell

1981-1986

Plating & Surface Finishing Engineer

Introduced electroless plating of palladium, nickel-boron, nickel-phosphorous process.

•

Devised improved plating fixtures and chemistry for gold plating, resulting in $10K annual

•

savings.

Implemented water saving program resulting in $40,000 annual savings.

•

Initiated metals reclamation for silver and cadmium, resulting in $50,000 annual savings.

•

Education Summary

B.S. in Chemistry, University of Wisconsin-Parkside, Kenosha, WI.

•

Graduate chemistry courses at University of Wisconsin-Milwaukee.

•

Graduate courses in Semiconductor Physics/Thin Film Technology, Northern Illinois

•

University, 1985-1986.

•

C Programming Class, Cray Research, 1996.

•

Programming in Perl (with Randal Schwartz), Cray Research, 1997.

•

Electrical Issues in Packaging, Georgia Tech,1997.

•

Linear Circuits I, University of Minnesota, 1998.

•

Electrical Grounding and Shielding, National Technological University, 1998.

•

Publications

M. Dibbs, P. Garrou, C. C. Chau, Y. So, D. Frye, J. Wagner, J. Ousley, G. Baugher, J.

Santandrea, G. Connor, J. MacPherson, G. Adema, P. Dean, L. Schaper, R. Eden, and R.

Sands, "Development of Seamless High Off-Chip Connectivity," Proc. 1997 Int'l. Symp.

Microelect., pp. 138-143, 1997.

Contact this candidate