Design Electrical Engineering

Yang Zhang **** Phaeton Ct., Plano, TX, *****

Phone: 214-***-**** Email: ***************@*****.***

OBJECTIVE

To obtain a job/internship position in Analog/Digital/RF/Power Integrated Circuit Design/Testing

EXPERTISE

Cadence design/layout flow; IC characterization; High speed transceiver design

EDUCATION

THE UNIVERSITY OF TEXAS AT DALLAS, Richardson, Texas 2010 ~2013

Master and Research/Teaching Assistant in Circuits of Electrical Engineering, GPA: 3.67

XI'AN JIAOTONG UNIVERSITY, Xi'an, China 2006 ~ 2010

Bachelor of Electrical Engineering, GPA: 3.55

MAJOR COUSES

Analog IC Design; Advanced Analog IC Design; High-Speed Data Communication Circuit;

Power Management Circuits; Energy-Harvesting, Storage and Powering for Microsystems;

Data Converters; RFIC; VLSI Design; Digital Signal Processing; Random Processes;

Hardware Modeling Using HDL; Linear Systems and Signals; Computer Programming with C++;

Principles and Application of Microcontroller; Power Electronics; Design of Electronics System;

RESEARCH & PROJECTS

Design and Fabrication of 5 Gbps Power Saving Within-Pair Skew Compensator (2011~2013):

Composed of training circuit & compensation circuit;

Training circuit: composed of fixed delay, skew detector & switch selector, determines signal paths;

Compensation circuit: two topologies, adjustable delay line & cross-connected phase blender;

Fabricated in ST 0.13µm CMOS, achieves 200ps ( 1 unit interval) compensation range for 5Gbps differential data, consumes 13.2/11.2mw with 1.2V supply and occupies 1 mm2 chip size.

Design of 10 Gbps Continuous-Time FFE/IIR Filter for High Channel Loss Equalization (2013):

FIR filter: Composed of active inductor delay line, MDAC and Cherry-Hooper transimpedance load;

IIR filter: Composed of current subtractor and delay line shared with FIR filter, largely reduce 1UI ISI;

Active inductor load linear equalizer is applied to largely reduce 2UI ISI and multi-stage output driver is used for better eye opening swing; Matlab program is designed for tap coefficient adaptation;

Will be fabricated in ST 0.13µm CMOS, achieves 35dB channel loss equalization at the data rate of 10Gbps, consumes 20mw with 1.2V supply and occupies 1 mm2 chip size.

Low Drop-Out Voltage Regulator (LDO) with Q-Reduction Technique (0.35µm CMOS):

LDO: 1.5V input with 0.2V dropout voltage, 1~100mA load current, Quiescent current < 60µA, settling time < 3ns, undershoot/overshoot < 90ms, Q-reduction technique applied to minimize the on-chip capacitance, Feedforward block and Miller capacitor used for better stability;

Bandgap voltage reference: temperature invariant output of 0.5V with temperature coefficient < 4.2ppm/0C.

Efficient Rectifier and Charge Pump for Micro-Scale Energy Harvesting (0.13µm CMOS):

AC input: 900MHz, 0.5V, DC output: 7V;

Rectifier: combination of cross-connected and diode bridge rectifier topologies to reduce leakage current to achieve over 30% power conversion efficiency;

DC-DC charge pump: modified Dickson’s structure for better reliability.

10-Bit, 300MHz Pipelined ADC (0.25µm CMOS):

60dB gain, 2V peak to peak swing and 1.2ns settling time 2-stage operational amplifier used to construct residue amplifier; 4 stages of 2.5bit sub-ADC and 1 flash to generate 10 bits after digital error correction; Sampling frequency = 300MHz, ENOB > 9.3 with input frequency varies from 10MHz to 150MHz.

100MHz Charge Pump Frequency Synthesizer (0.35µm CMOS):

Bootstrapping charge pump applied to suppress charge sharing; level shifter, CS amplifier and I/V converter used with 4-stage ring oscillator as VCO to achieve lock under rail-to-rail initial voltage; settling time < 2.2ns, skew & jitter < 1.5ns, KVCO > 80MHz/V under lock condition

Others:

Layout and Testing of 5-Bit 1GHz 2-step ADC with Meta-Stability Detector (IBM 0.13µm BiCMOS);

Fast Settling Auxiliary Amplifier with Slow Settling Damping Technique (0.25µm CMOS);

LTE Direct Conversion Receiver Design (0.18µm CMOS);

VLSI Design of 32-Bit ALU and 4 Tap FIR Filter

HDL design on vending machine and FIR filer

TOOLS & SKILLS

Cadence Analog Artisan, Virtuoso, Agilent ADS, Synopsys, Encounter, Protel, Modelsim, VHDL/Verilog, Spice, Matlab, FPGA, BERT, Oscilloscope, Signal Generator, Pattern Generator and Logic Analyzer

LANGUAGE

English/Mandarin

EXTRA-CURRICULUM ACTIVITIES

Soccer player in Xi’an JiaoTong University Soccer League (2008)

Organizer of Xi’an JiaoTong University Soccer League (2009)

Host of Mid-Autumn Ceremony of University of Texas at Dallas (2010)

VISA STATUS

F-1 Student

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