Engineer Design

Maneesh Kumar Pandey

Analog Characterization Engineer - Freescale Semiconductor

Noida - India

*******.*****@*****.*** - 981*******

Technical Leader

Work Experience

Analog Characterization Engineer

Freescale Semiconductor - Noida, Uttar Pradesh

August 2011 to Present

Leading the USB3.0 Characterization for LS-1 & LS-2 SOC & USB2.0 Characterization for T2080 &

P1010 SOC’s.

Lead the USB2.0 Characterization on three SOC's (P3041, P5040, T4240).

Managing the team for above mention projects

Got the Operational Excellence Award for USBPHY-IP CZ on above mentioned SOC

Sr. Design Engineer

Freescale Semiconductor - Noida, Uttar Pradesh

July 2006 to July 2011

Characterizing the Antenna PLL & DDR PLL for complex, multi-layer Networking processor (P9131,

P1010, P3041. MPC5121e etc)

Responsibilities include study and discuss with designer about concern interface to define the all

components of for preparing the characterization plan, perform the characterization at all defined PVT and

publish report with all issues.

Involved in hardware design, board bring-up, and board validation

Responsibilities include Defining board specifications, component selection, datasheet study, board

schematic review. PCB layout review, board validation and testing, support to software/hardware IP team

& customers and documentation.

Validated USB-OTG, USB2.0, I2C, USB Battery Charger.

Responsibilities include study and discuss with designer about concern interface to define the all

components of for preparing the characterization plan, perform the characterization at all defined PVT and

publish report with all issues.

Involved in hardware design, board bring-up, and board validation

Responsibilities include Defining board specifications, component selection, datasheet study, board

schematic review. PCB layout review, board validation and testing, support to software/hardware IP team

& customers and documentation.

Post Silicon validation of USB-OTG, USB2.0, I2C

Lead the USB validation & Characterization: Responsibilities include to validate the Digital & Analog

block of a USB 2.0 HS Test-chips as well as in different products from different group (i.e. Networking,

Automotive, wireless), prepare an excel which gives the full status of all tests and with complete report

along with issues & results.

System level testing of USB-OTG, USB2.0 products as a host, device and also dual role

Responsibilities include Installing the LTIB-based BSP on a host development system, Run LTIB to

build target images needed for deployment, Deploy the built image to the P1010RDB MPC5121eDS,

P1020RDB, P5020DS board, Boot Linux on the P1010RDB MPC5121eDS, P1020RDB, P5020DS board.

Observe the USB LS/FS/HS enumeration process where an external USB device is connected to the

DUT working as Host and vice versa.

Perform in house USB-IF Compliance certification Testing & Also involve in getting USB-IF compliance

certificate for product MPC5121e.

Responsibilities includes getting USB-OTG compliance certification from external lab for which

performed the In-house USB-OTG compliance testing, so involve in preparation of compliance test plan,

instruments/cables/ other item list require for compliance testing and information regarding lab.

Designed innovative setup for validation of digital and analog module of ULPI-PHY IP.

Automated (in LabView) the USBPHY-IP setup for validation of digital and analog test cases

Verification of USB2.0, USB-OTG design and HDL Simulation

Responsibilities include Simulating the device using Synopsys VCS, run the regression for USB2.0 and

USB-OTG design.

Received appreciation from customers on above projects done.

ASIC Verification Engineer

AfilaTech India Pvt. Ltd - Bangalore, Karnataka

March 2006 to June 2006

Involved in hardware logic design, Verilog RTL design for FFT and OSCAR processor

Responsibilities include designing, RTL coding and development using Verilog, synthesis, Hardware

specification study.

On-site work Involved creating test cases and Documentation.

Education

M.Tech in ASIC Design

Motilal Nehru National Institute of Technology (MNNIT) - Allahabad, Uttar Pradesh

2002 to 2004

Skills

Hardware Skills: Analog characterization, Post Silicon Validation, Compliance Testing and System Level

Testing, Automation and RTL Design. Hardware

Tools: Digital Storage Oscilloscope, Temptronics (X-STREAM 4310), Logic analyzer, Spectrum Analyzer,

Data Generator, Waveform Generator, TDR (Time Domain Reflecto-meter), BERT Scope.

Software Skills: Installing/Uninstalling the BSP (board support package) to the Host System, Building the

image files with default configurations, Reconfiguring and recompiling the images.

Software Tools: CCS-LLD, Real View Debugger, nSim. LabView 8.5, USBCV, HSET, Allegro Physical

Viewer.

Interface Knowledge: USB2.0, USB-OTG, ULPI, PLL, I2C, USB3.0, SERDES.

Languages Used: Verilog, Tcl, 'C', Python

OS: Windows, UNIX (Sun Solaris), Linux.

Soft skills: Innovative and creative, Possess analytical and communication skills.

Awards

Bravo Award-Technology Award for Validation and Characterization

Technology Award for Validation and Characterization of industry first C45SOI USBPHY-IP

Employee Excellence Award

Received the Employee Excellence award for completing 5 year in Freescale

Figo-Operational Excellence Award

Operational Excellence Award for USBPHY-IP CZ on T4240, P3041, P5040 SOC

Patents & Disclosures

Defensive Publication

A Novel Nanoscale Standard Cell Look up Table Characterization Tool Using Robust Semi

Empirical Delay Model

United States

Gaurav Agrawal Shwetank Shekhar Maneesh Kumar Pandey

Publications

USB Validation Challenges on C45SOI & C28nm Technology Products

Maneesh Pandey, Atul Gupta, Shwetank Shekhar, “USB Validation Challenges on C45SOI & C28nm

Technology Products” published in Microprocessor Test & Verification (MTV 2013) Austin, Texas, USA

An Approach for In-House USB2.0 Electrical Compliance Testing on nanoscale SoC

Maneesh Pandey, Shwetank Shekhar, Gaurav K Agarwal, Nitin Saxena, “An Approach for In-House

USB2.0 Electrical Compliance Testing on nanoscale SoC” published in Microprocessor Test & Verification

(MTV 2013) Austin, Texas, USA

USB 3.0 Speeds up Performance on External Devices: With Optimized Power Efficiency &

Backwards Compatibility

http://www.design-reuse.com/articles/32738/superspeed-usb-3-0-overview.html

3 September 2013

Maneesh Kumar Pandey, Neeraj Jain, Sudhanshu Mishra, "USB 3.0 Speeds up Performance on External

Devices: With Optimized Power Efficiency & Backwards Compatibility" Published online at Design &

Reuse.

A Novel Approach for USB2.0 Validation on System on Chip

Maneesh Pandey, Shwetank Shekhar, Gaurav K Agarwal, Nitin Saxena, Joginder Singh, “A Novel

Approach for USB2.0 Validation on System on Chip” published in IEEE International Conference on

Computing, Communication and Networking Technologies (ICCCNT 2013)

A Novel USBPHY-IP Validation Framework

Maneesh Pandey, Shwetank Shekhar, Gaurav K Agarwal, Amit Sinha, “A Novel USBPHY-IP Validation

Framework” published in IEEE International Conference on Control, Computing, Communication and

Materials (ICCCCM 2013)

Validation of USB Peripheral Checklist: A challenging Requirement for SoC

Maneesh Pandey, Neeraj Jain, Shwetank Shekhar, Amit Sinha, “Validation of USB Peripheral Checklist: A

challenging Requirement for SoC” published IEEE International Conference on Multimedia, Signal

Processing and Communication Technologies (IMPACT 2013)

Post Silicon Debugging Approach for USB 2.0: Case Study of Enumeration

Shwetank Shekhar, Maneesh Pandey, Gaurav K Agarwal, Nitin Saxena, “Post Silicon Debugging

Approach for USB 2.0: Case Study of Enumeration” IEEE International Conference on Computational

Intelligence and Communication Networks (CICN 2013)

IRIS Recognition for Personal Identification

Harsh Vikram Singh, Maneesh Pandey “IRIS Recognition for Personal Identification,” Proc. 4th

International Conference on Quality, Reliability and Infocom (ICQRTI- 2009), University of Delhi,

NEW DELHI

Additional Information

USB-IF Compliance Certification from External LAB for MPC5121e product for USB-OTG

Performed complete testing of product P1010RDB (from Functional Validation to compliance Testing) i.e.

from functional validation to Analog Characterization to System Level testing to In-house Compliance

Testing. Also validated the digital and analog block of USB-IP

Innovative Setup designed for digital and analog testing of USBPHY-IP using FPGA.

Performed complete testing of product P1010RDB (from Functional Validation to compliance Testing) i.e.

from functional validation to Analog Characterization to System Level testing to In-house Compliance

Testing. Also validated the digital and analog block of USB-IP

Member of International Association of Engineers (IAENG) (August 2011 to Present)

Participated in Delhi Half Marathon twice (Received certificated & Medal for the same).

Always Participated in CRY Cooperate Cup tournament for soccer matches from Freescale soccer team

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