Engineer Project
Resume:
Sonal Powar
***.****@*****.***
PERSONAL DETAILS:
Father’s Name : Mr. Shitalanath Patil
Spouse Name : Mr.Kamalakar Powar
Sex : female
Marital Status : Married
: 30th oct 1989
Date of Birth
Languages Known : English, Marathi and Hindi
Nationality : Indian
Permanent Address : B-5, Highway Park colony,
Near Mahalaxmi Hall,
Rajesh Motors,
Kolhapur 416003
Maharashtra.
OBJECTIVE
Seeking assignment in IP/SOC verification where I can effectively contribute my skills as Verification professional,
possessing competent technical skills.
Executive Summary
• Having total Experience of 2 Year and currently working in Wipro Technology as VLSI project Engineer. The
responsibility includes analyzing the USB 3.0 protocols & Developing the testbench Environment for the same
using System verilog & UVM
• Enriched with the ability to learn new concepts & technology within a short span of time. Possess Technical
Knowledge of VLSI, system verilog, Embedded Systems, C Programming, UNIX Operating Systems and Digital
Systems.
• Having good experience in VHDL,System Verilog,verilog,Simulations & Synthesis
• Had 3 months of Verilog, System Verilog and UVM training in Wipro.
EDUCATIONAL QUALIFICATIONS
• 4th Rank in University in BE.
• Bachelor of Engineering (81%), Electronics, KIT College of Engineering, Shivaji University, Kolhapur, 2011.
• Senior Secondary Education (87.33%),Vivekananda College,Kolhapur,2007
• Matriculation (86.40%), Usharaje High school, Kolhapur, 2005.
WORK EXPERIENCE
Project Engineer Oct 2011 – Present
Wipro Technologies Ltd., Bangalore, Karnataka.
• 2 years of experience as Project Engineer in Verification at WIPRO VLSI.
Details of Projects Worked On
SOC verification (Smart Phone Apllication)
Project1:
Duration:
Description:
Role:
Contribution:
Team Size:
Technologies
Involved
Project2:
Duration: 6 months
Description: Tangier is the SOC developed for Smart phone application, handling
advance technologies such as Otg, HSIC,RIL protocol.
Role: Level 1 Verification Engineer
Contribution: Analysing USB 3.0, USB 2.0 Protocols.
HSIC, Otg, UTMI, ULPI, EHCI interfaces.
Writing sequences and testcases to verify the functionality of HSIC
andOtg2,otg3
Team Size: 12 members
Technologies System Verilog and OVM.
Involved
SKILLS AND EXPERTISE::
Development of Verification components for verification of SOC/IP/ASIC Blocks
Development of Verification environment in System Verilog + [UVM] with active role in Verification
Guide/Plan, Coverage analysis, Simulation/Regression Scripts, and Test Suite.
Strong understanding of USB3.0 Protocols Specialties.
System Verilog IP Test bench Environment in UMM,OVM
Development of all Verification components like Driver, Sequencer, Monitor, Agent in UVM .
Integration and usage of Verification IPs from Cadence and Denali.
Basics of System Verilog Assertion and coding of assertion.
Internship
Wipro Technologies Ltd, Bangalore Karnataka.
Project Name: Stopwatch development and verification
Duration: 1week
Team Size: 2
Client: Wipro
Description of Project: Stopwatch should be implemented as a counter which starts from 0 and stops at 999 if
not interrupted by the user. It should be capable enough to resume its operation from the last count when it was
actually stopped by the user.
Technologies Involved: Verilog
Role: Verification.
Responsibility: Design, Coding, Unit testing
AWARDS and ACHIEVEMEN
• Certified UCF 1.1 and UCF 2.1 VLSI Verification “Unified Competency Framework” of WIPRO.
Protocols.
USB 3.0
OCP
AHB
Tools
VNC
VCS
ModelSim.
Pureview
Interests
VHDL
VERILOG
System Verilog
UVM
OVM
ACTIVITIES OTHER THAN PROJECTS:
• Organized outing for VLSI dept. in WIPRO Bangalore.
• Organized birthday celebrations of my team.
Contact this candidate