VLSI design

CURRICULUM VITAE

SONIYA

M.tech (VLSI Design)

Contact no.: 827-***-****

Email: ******.*****@*****.***

OBJECTIVE

Seeking a challenging position to utilize my skills and creativity in field of VLSI Domain which will offer professional growth while being innovative and resourceful. EDUCATION BACKGROUND

Academic Details:

COURSE

BOARD/UNIVERSITY

PASSING YEAR PERCENTAGE

M.tech

(VLSI Design)

NIT Jalandhar Pursuing

(2017-2019)

77.4 %

(till 3

rd

sem)

B.Tech

(ECE)

Uttarakhand Technical

University, Dehradun

2014 73.33%

Diploma

(Electronics)

BTEUP, D.J. Polytechnic

Baraut Baghpat

2011 76.89%

PROJECT PROFILE

M.Tech

Worked on Thesis “Dual Source Vertical Tunnel Field Effect Transistor: Simulation and Analytical Modeling” using silvaco atlas tool.

Layout design of CMOS Inverter using cadence virtuoso B.Tech

Worked on a project “Home Appliances Automation Control Using Mobile’’. Diploma

Worked on a project “AM Receiver”

TRAININGS/ CERTIFICATIONS

One-week short term course on “Research Trends in VLSI Devices and Circuit Co- Design” in NIT Jalandhar.

TEQIP –III sponsored short term course on “Current Avenues of Research in Electronics and Communication Engineering” in NIT Jalandhar.

A one-month summer training on “Power Transmission” in power transmission Corporation of Uttarakhand Ltd.

A Three-week summer training on “Basic Introduction of CNC & PLC Drive” in Bharat Heavy Electricals Ltd Ranipur, Haridwar. RESEARCH PUBLICATIONS

Journal

1. Soniya, Girish Wadhwa, Shailendra Singh and Balwinder Raj, “Design and Analysis of Dual Source Vertical Tunnel Field Effect Transistor for high Performance” submitted in Integration, the VLSI Journal. Submission no: VLSI_2019_224. 2. Soniya, Balwinder Raj, Shailendra Singh and Girish Wadhwa, “An Analytical Modeling for Dual Source Vertical Tunnel Field Effect Transistor” Accepted by International Journal of Recent Technology and Engineering, Paper ID - B2253078219.

Conference

Soniya, Shailendra Singh and Balwinder Raj, “Performance Investigation Of Dual Source Vertical Tunnel Field Effect Transistor for Steeper Sub-Threshold Slope” presented a paper in International Conference on Production and Industrial Engineering (CPIE 2019). Paper ID: CPIE-2019_214.

TECHNICAL SKILLS

Programming Languages Basic of Verilog

Software Xilinx vivado tool, Cadence virtuoso Tool, Silvaco Atlas tool STRENGTHS

Confident, Honest, Self-motivated, Positive attitude and easily adaptable to new things. Hardworking and Capable of working in team or individually and take up responsibility. PERSONAL PROFILE

Father’s name : Roshan Lal

Gender : Female.

Date of Birth : 15-06-1991.

Marital status : Single.

Languages known : English and Hindi.

Hobbies : Listening Poems, Travelling, helping old & disabled, playing chess Permanent Add. : Street-teergran, Town-Charthawal, Distt.-Muzaffarnagar (U.P) 251311. DECLARATION

I hereby declare that the above information is true to the best of my knowledge.

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