Siva Pandi. V

FPGA DESIGN ENGINEER

Email: ac9v9k@r.postjobfree.com Contact: +91-701*******

Career Objective

To work in a challenging position in a semiconductor company, where my professional and technical skills can be put to maximum use and contribute towards the goals of the organization and personal development.

Summary

Total 5 years of experience in VLSI domain (RTL Development & FPGA Design Engineering).

Knowledge of VHDL, Verilog programming developments.

Excellent Script commands over Perl, Tcl and shell.

Knowledge of FPGA design principals and RTL developing and debugging tool for FPGA (Vivado for Xilinx EDK, Xilinx ISE, Xilinx chip scope pro, schematic, IP core )

Done RTL synthesis, XDC constraints design, timing closure, CDC analysis, design implementation process, static timing analysis, design synthesis DRC analysis and IP integration with RTL design and Prototyping using virtex-7 device.

Hands on experience in working on multiple FPGAs such as Spartan 3, Spartan 3E, virtex 7 board and communication protocols like SPI,I2C and UART.

Worked build environment run time wise reduction (Partial reconfiguration & Hierarchical design).

Done Migration of 7’series to Ultra Scale Device.

Basic understanding of PHY layer (LTE).

Worked on FPGA hardware wise integration:

Integrate PSRAM component,

Integrate PROM component,

Integrate Digital architecture.

Experience Summary:

Organization

Designation

Duration

MBIT WIRELESS

FPGA Design Engineer

April 2018 - Till

Crisp India System Pvt Ltd

FPGA Hardware Design

June 2016- April 2018

Elysium Technologies Pvt Ltd

VLSI RTL Programmer

June 2014 – June 2016

Technical Skills

Core : FPGA bring-up for wireless modem chip-set, FPGA

Design/Validation, FPGA design based RTL development.

Software Packages : Vivado 17.4, Synopsys, Xilinx ISE IMPACT 14.3, Modelsim 10.1,

Altera Quartus, MATLAB 2015a.

Programming : VHDL and Verilog.

Script : Perl, Tcl, Shell.

Working projects as FPGA design Engineer

Task

Partial Reconfiguration & Hierarchical Design

Tools

Vivado 17.4

Accomplishments

Analysed design flow, Derived the necessary requirements for PR & HD implementation.

Scripting framework with PBLOCK XDC constraints for the build flow automation.

Pblock arrangement and partial generated bit file.

Task

FPGA bring-up & design/validation

(XDC constraints & property update & DRC report analysis)

Tools

Vivado 17.4

Accomplishments

Clocking requirement wise changes and XDC timing and physical constrains for both the synthesis & implementation phases.

Congestion, design analysis, timing & utilization reports, placement rules and set necessary property and RTL changes for synthesis and implementation process.

DRC reports and observed HOLD violation in some of specified hierarchical path. Applied BUF like BUFH, BUFHCE and BUFR insert clock path.

Task

Migration of Ultra Scale Device

Tools

Vivado 17.4

Accomplishments

Reviewed the migration details about 7’series to Ultra scale device.

Analysed clocking and CLB wise changes on Ultra scale target devices.

Scripting work with necessary clocking constraints for Ultra scale devices.

Task

Build Environment based script wise development

Script

Perl, Tcl, Shell

Accomplishments

Critical issues/warnings were reported in the build log compare to previous log file.

Scripting work for automating the new warning report compare to previous report.

Focused for review synth, place and route design report WNS, WHS slack and their clock details through single report.

Working projects as Programmer

Project Name

A NEW DATA TRANSFER METHOD OF SIGNAL RICH ART CODE MODULATION FOR MOBILE DEVICES

Role

VLSI Programmer

Language

VHDL & Verilog, Matlab code.

Tools

Xilinx 14.5 & Mat lab 2013a & Modelsim 10.0c.

Description:

Information hiding is major part of a wide spectrum of methods that are used to make data difficult to notice. This system is to get Information data bits and create the data matrix pattern image. This pattern image embedded to any one selected image using rich art code modulation methodology.

Project Name

ECONOMIZING TSV RESOURCES IN 3D

NETWORKONCHIP DESIGN

Role

VLSI Programmer

Language

VHDL, Verilog.

Tools

Xilinx 14.5 & Altera Quartus & Modelsim 10.0c.

Description:

The combination of 3D integration and NoC soon becomes most effective ways to on-chip communication fabrics for multicore designs like MPSoCs. This system is following a torus topology based internal router node connection for XYZ directions and also implement the shortest path identification for 3D-NOC structure using gray code, Ripup reroute, adaptive CS, PS, VCS algorithm.

Educational Background

Bachelor of Engineering (Electronics and Communication department, RVS college of Engineering and Technology) 2014, Anna University Chennai with 7.467 CGPA.

Personal Information

Date of Birth / Age : 1st June, 1993 / 26 years.

Marital Status : Single

Languages Known : English, Tamil.

Nationality : Indian

Current Location/Relocate : Chennai / any location in India.

Notice Period : 3 month

Declaration

I hereby declare that the above-mentioned information is correct up to my knowledge and I bear the responsibility for the accuracy of the above-mentioned particulars.

Place: Chennai

(Siva Pandi V)

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