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Engineer Power Plant

Location:
Moorpark, California, United States
Posted:
July 14, 2019

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Resume:

JAGADEESWARA RAO KANDI

**** * ********* ****, ***#8 ac9tms@r.postjobfree.com

Los Angeles, California-90064 +1-361-***-****

OBJECTIVE

Electrical Engineering graduate with high motivation, enthusiasm, academic excellence and with 2 years of experience in Design of ASIC/SOC. Masters graduate major in Control Systems and Research Experience with robots to implement Flocking Behavior. EDUCATION

Master of Science - Electrical Engineering GPA: 3.7 Texas A&M University- Kingsville, TX Dec 2017

Bachelor of Technology in Electronics and Communication Engineering GPA: 3.6 VR Siddhartha Engineering College, Andhra Pradesh, India April 2012 CERTIFICATIONS

Passed PE (Professional Engineer) Exam in Electrical and Computer: Electronics, Controls and Communications with a Passing Score of 81 out of 100 from Texas Board of Professional Engineers (TBPE). October 2017

Certified Engineer in Training (EIT) from Texas Board of Professional Engineers (TBPE) in Electrical and Computer. June 2017

WORK EXPERIENCE

Niche Biomedical Inc (Los Angeles, USA) Jan 2019-Present Electronics Engineer

Spinal Cord Stimulator

The project is about development of Non-Invasive Spinal Cord Stimulator for paralyzed people. Roles and task include:

o Designed and simulated current driver circuit using LTSPICE. o Selected components for the design through data sheets. o Tested the designed current driver circuit on breadboard and characterized it’s features. o Integrated current driver circuit with ASIC for testing. o Developed impedance measurement circuit for electrode impedance measurement. o PCB Layout design of the current driver circuit. o Experience with Electronic test equipment (CRO, Power Supply, Function Generator and Soldering tools)

Signal processing of patient posture data

The project is about development of algorithm to present patient posture on GUI Roles and tasks include:

o Develop algorithm to use voltage data from flex sensor to output angle measurement of patient posture. The algorithm should include acceptable Sensitivity and SNR preliminary controls. o Create real time visual of angle measurement in JavaScript and HTML. o Research on Spinal Cord Stimulation technology, Vital sign processing Technology for EMG, accelerometer/gyroscope, heart rate, blood pressure and respiratory rate measurement. o Research on Sensors (Flex, Bend, MEMS etc.) and selection of IC’s for signal processing (Data Acquisition). CloudBig Technology (Bangalore, India) Mar 2015-Dec 2015 Design Engineer

APB Bridge Design:

The project is about designing bridge which converts from AXI4.0 Lite transactions to APB transactions. Roles and task include:

o Created a design document plan, describing various blocks of the design and an abstract way of their implementation. o As a part of the project, first an APB bridge was designed in Verilog HDL which converts from AXI4.0-Lite to APB transactions and basic block level testing is done in Verilog.

APB Slave Design:

The project is about design of APB Slave.

Roles and task include:

o Designed the RTL for APB slave and verified it in Verilog using directed tests. Singhal Enterprises Pvt.Ltd (Chattisgarh, India) Jan 2013-Feb 2015 Electrical Graduate Engineer

Worked as an Electrical Graduate Engineer Trainee (GET) for 1 year and Graduate Engineer for 1+ years in Electrical and instrumentation department at 16 MW Thermal Power plant.

Maintenance and Monitoring of Ash Handling System. CMOS Research Labs. (Vijayawada, India) Jan 2012-Dec 2012 VLSI Developer intern.

Design of Three-Way Round-Robin Arbiter:

The project is about designing an Arbiter that accepts data from each microprocessor and arbitrates which one is granted access to the RAM at any one time.

Roles and task include:

o Created a design document plan, describing various blocks of the design and an abstract way of their implementation. o The round robin priority access to the RAM from each microprocessor is modeled using a state machine in Verilog HDL. SELECTED ACADEMIC PROJECTS

Adaptive Control of Robotic Vehicles to self-align into an Equilateral Triangular Formation

(M.S Thesis Research) Dec 2017

o Understood the Modeling of Wheeled Robot using Kinematic Bicycle Model. o Developed and implemented an Algorithm for specified path in Matlab by using Waypoint Tracking Technique for a single Robot with different initial conditions and different number of waypoints. o Developed and implemented an Algorithm for a single Robot to follow a specified track in Matlab. o Developed and implemented an Algorithm in Matlab for multiple Robots to follow the defined path in flocking behavior without collision for different initial positions of Robots. o Developed and implemented an Adaptive Algorithm in Matlab for three Robots following a specified path in Equilateral Triangular Formation by using Local Distributed Control Algorithm.

State Feedback Controller, Observer and LQR Design for Inverted Pendulum o Modeling of the Inverted Pendulum and obtained Linear State Space Representation. o Controllability and Observability of the system is verified in Matlab. o Designed an Observer for the system and verified it using Matlab. o Designed State Feedback Controller using Optimal Control Theory for LQR (Linear Quadratic Regular).

MRAC Controller Design for Inverted Pendulum (Project) Dec 2016 o Selected a Reference Model for the Inverted Pendulum System to meet the vertical angle (< 0.35 rad) for a unit step input.

o Design and Implementation of Adaptive laws and Control laws in Matlab to meet the requirements in Model Reference Adaptive controller (MRAC) design.

Design and synthesis of a controller for the vending machine using FSM in an FPGA device: Created and synthesized a VHDL model for the vending machine and demonstrated its operation using a Cyclone V FPGA in DE1-SoC board.

Embedded system hardware design: Designed an embedded system hardware in both VHDL and Verilog for the following specifications; 512Kbyte RAM, 256Kbyte EPROM, 2CCD Camera Controllers and one serial I/O with appropriate device addressing (memory mapping).

General purpose embedded system design: Designed a general purpose embedded system for Cyclone FPGA for the following minimum system requirements; NIOS II microprocessor core with exception vectors & reset in flash memory, 4Kbytes d-cache, on-chip RAM-32Kbytes, off-chip RAM-2Mbytes, CFI flash memory interface-8Mbytes, SDRAM Controller- 16Mbytes, UART-RS-232(8 bit even), Timer, Ethernet interface, Parallel I/O(PIO)-4 bit inputs(push-button), 4bit outputs(LEDS), LCD screen interface.

TECHNICAL SKILLS

Hardware Languages : VHDL, Verilog HDL, System Verilog Software Languages : C, Matlab, LTSPICE, Easy EDA

EDA Tools : Xilinx ISE, Quartus, ModelSim.

Protocol knowledge : UART, AXI4.0 Lite, APB4.

ACHIEVEMENTS

Secured All India Rank of 8,015/216,367 with a score of 532 in GATE 2014.

Secured State Rank of 182/18,252 in ECET Exam Conducted By State Board of Technical Education, Andhra Pradesh-2009.



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