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Design Engineer Engineering

Location:
Mississauga, Ontario, Canada
Posted:
July 14, 2019

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Resume:

ZAREEN JAHANGEER

*** ******** ********, ***********, **, L5C 3W1

819-***-**** ac9tlr@r.postjobfree.com

CAREER OBJECTIVE

Self-driven recent university graduate in electrical engineering with strong knowledge in digital, analog and RF circuit designs. Innovative and talented individual committed to provide unexceptional performance to your company. Believe in pushing the boundaries through creativity, hard work and responsibility at a workplace. EDUCATION

• Master’s in Electrical and Computer Engineering 2017-2018 Carleton University, Ottawa, ON

GPA: 3.6/4

Courses: Radio Frequency Circuit Design, Microwave & Millimeter wave IC Design, Signal Processing Electronics, Signal Integrity in High Speed, High Speed Low Power VLSI and VLSI Design.

• Bachelor’s in Electrical Engineering 2012-2016

Osmania University, Hyderabad, India

GPA: 8.74/10

Courses: Analog Electronics Circuits, Basic Circuit Analysis, Digital Integrated Circuits and Applications, Linear Integrated Circuits and Applications, Network & Transmission Lines, Pulse Digital and Switching circuits. SKILLS

• Designing Tools: Cadence Virtuoso, Cadence Layout (DRC, LVS and Extraction), Xilinx ISE, Xilinx Vivado HLS, Key-sight ADS, HSPICE, MATLAB, Mentor Graphics, PSPICE.

• Hardware: FPGA Board, Microcontrollers and Microprocessors

• Programming Tools: Python, C/C++, Embedded C, Verilog and VHDL

• Operating System: Linux, Windows, Microsoft, Unix

• Soft skills: Public speaking, Leadership, team player ACADEMIC PROJECTS

• Double Balanced Gilbert Cell Mixer September 2018 – April 2019 Carleton University, Ottawa, ON

- Implemented gilbert cell mixer at 65nm CMOS technology for Radio Frequency of 7.8GHz and Intermediate frequency of 200MHz in Cadence Virtuoso. Demonstrated proficiency with RF circuit design simulation, schematic

design and layout tool.

- Caliber DRC, LVS and PEX tools were used for layout design and extraction.

- Results of schematic design and post layout design met the requirements of the design.

• Differential & Two stage Operational Amplifiers September 2018 –December 2018 Carleton University, Ottawa, ON

- Designed two stage operational amplifier and telescopic cascode differential amplifier in 45nm technology AMS kit using Cadence Virtuoso.

- The layouts were implemented using different techniques such as common centroid, dummy transistors and interdigitate methods for better matching. Assura DRC, LVS and extraction tools were used for design of the layout.

- The post layout simulations of the circuit met the specified requirements for the design.

• Distributed and Feedback Amplifier January 2018 –April 2018 Carleton University, Ottawa, ON

- Amplifiers were designed using PIHO GaAs kit from Keysight Advanced Designed system (ADS) where EM model was developed for input and output matching networks in ADS momentum and EM Co-Simulation was used on the

layout.

- GaAs MMIC Distributed amplifier was designed to achieve a stable gain in the frequency range of 1-65GHz using K and m-derived section of the artificial line to give a gain of at least 12 dB.

- GaAs parallel feedback amplifier at center frequency of 28.5 GHz was executed for a gain of 14dB and Noise figure of 1.5dB.

• Radio Front-End Circuits January 2017 –April 2017 Carleton University, Ottawa, ON

- Radio Front-End Circuits were implemented using IBM 130nm CMOS technology in the Cadence Virtuoso.

- Cascode CMOS Low Noise Amplifier was implemented at the center frequency of 7.8GHz.

- Double-Balanced Down conversion Gilbert cell Mixer was designed at a radio frequency of 7.8 GHz, and the intermediate frequency of 200 MHz.

- Cross-coupled LC Negative Gm Voltage Controlled oscillator was designed at an oscillating frequency of 8 GHz.

- A Class AB Power Amplifier with the center frequency of 7.8 GHz was implemented with the supply voltage of 1.8V in a 50 Ohms system.

• Direct Down Conversion Receiver July 2015 –April 2016 Osmania University, Hyderabad, India

- Implemented the Front-End Direct down Conversion Receiver for WiMAX application at 3.5 GHz center frequency as a final year undergraduate project in a team of 3 students.

- Designed a Gilbert cell Mixer at 3.5 GHz Center frequency (RF) and 3.5 GHz local oscillator (LO) frequency, as the Direct down Conversion Receiver does not have an Intermediate Frequency (IF) using TSMC 180nm CMOS technology

- The Gilbert cell Mixer was implemented using TSMC 180nm CMOS technology in the Cadence Virtuoso with a gain of 8.44 dB, Noise Figure of 8.18 dB, 1-dB compression point of -8.31 dBm and the IIP3 of 3.33 dBm.

• Bidirectional 4-bit Johnson Counter September 2017 –December 2017 Carleton University, Ottawa, ON

- Designed 4-bit counter Bidirectional Johnson counter on Spartan-6 FPGA kit using Xilinx ISE which was used as a synchronous decade counter. The design would work as an Up counter and Down converter depending on the state of the enable pin, and they can be reversed at any time by changing the state of the enable.

- Designed 4-bit data path operators such as ripple carry adder, carry look ahead adder and ripple borrow subtractor in Verilog and VHDL.

• Counters, Matrix Multipliers & Frequency Modulator September 2017 –December 2017 Carleton University, Ottawa, ON

- Implemented Counters, Matrix Multipliers and frequency modulator using Xilinx Vivado HLS.

- The source files and test benches for the above-mentioned modules are written in C/C++, then the code is simulated and synthesized to generate Verilog and VHDL code.

- Unique IP address is created for each design which can be translated to an FPGA board. EXPERIENCE

• Graduate Teaching Assistant September 2017 –December 2017 Carleton University, Ottawa, ON

- Acted as an instructor for fourth year undergraduate course “Digital Circuit Design” and illustrated Verilog, VHDL and Xilinx ISE tools in computer aided design environment.

- Constructively managed and organized labs for 3 hours per week and provided supervision through counselling and tutoring. Aided in developing manual content for the lab course.

• Internship at telecommunication corporation January 2014 –December 2014 Bharat Sanchar Nigam Limited, Hyderabad, India

- Perceived the working of different types of equipment and systems used in the telecommunication technologies.

- Examined connections between networks, telecommunications and system administration presently used at the industry. Rendered solutions for ongoing and forthcoming requirements of broadcasting and converged networks for countryside application

VOLUNTEER EXPERIENCE

• Volunteer Fundraiser September 2017 –December 2017 Carleton University, Ottawa, ON

- Actively organized and assisted events which accumulated a significant amount of funds for the CHEO foundation.

- Monitored the progress of charity drives and developed techniques to promote contributions.

• IEEE WIE (Women In Engineering) volunteer January 2014 –April 2016 Osmania University, Hyderabad, India

- Conducted workshops every once in a year to impart the practical knowledge and importance of computers to students from underprivileged schools. Raised funds for providing proper education for underprivileged children.

- Created awareness among girls about the importance of engineering, entrepreneurship and women empowerment.



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