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Assembly Language, Verilog HDL, Digital ECS, Analog Ciruits

Bhubaneswar, Odisha, India
June 29, 2019

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Aditya Kumar Prusty

Personal Data

Date of Birth: 26 March 1997

Address: Gopalpur, Raghunathpur, Jagatsinghpur District, Odisha Phone: 765-***-****


Career Objective

To work in an organization where I can freely and independently use my full potential and solve real life problems. Education


National Institute Of Technology, Rourkela

Gpa: 7.63/10

2014 Intermediate in Science,

B.J.B. Junior College

Percentage: 75.66

2012 Matriculation,

Saraswati Shishu Vidya Mandir,Baramunda

Percentage: 92.16


Home Automation May-August, 2017

This project involves making a smart home automation system which can monitor and employ to make home appliances auto- mated and drive them towards higher efficiency saving energy and time at low cost.

LED Flasher and LED classifier circuit October, 2017 - December, 2017 This project involved design a LED flasher and classifier circuit for locomotives.

Digital Speedometer for Diesel Locomotives October, 2017 - December, 2017 The main objective of this project was to design a Digital Speedometer for Medha/Siemens diesel locomotives in place of the present analog meters, so that the speed data gets less er- roneous and prevents accidents. The speedometer was designed by decrypting the event recorder data of the locomotive and dis- playing it using a single board computer.

CCTV Data Classification August, 2017 – Nov, 2017

This project was under the ’Smart City’ project assigned to the institute by MHRD. This project involved classification of large amount of video data acquired by the different CCTV cameras all around the city, mainly by those on the streets and roads. The data was classified as per the requirements using image process- ing.


FFT Processor Design Feb, 2019 – March, 2019

The main objectiive of the project was to design a FFT processor that computes 8 point FFT of 16 bit data signal. The FFT processor was designed in Verilog HDL and implemented in a FPGA. Controlling Heat Exchanger Control System July, 2018 – May, 2019 The main objectiive of the project was to design a mathematical model of heat exchanger system in SIMULINK and design vari- ous controller for set-point tracking and disturbance rejection. Simulations were done and the controllers were tuned to get best responses.

Work Experience

Intern at DRDO PXE 15 May-15 July, 2018

During this time at DRDO,studies involving Ballistic Instrumentation,Sensors and Piezo- electric devices are done and Microstrip patch antenna was designed. Technical Skills

General Programming: C, C++, Embedded Programming in Assembly level language, Verlog HDL Programming, Arduino Other Software: NI multisim, Tanner Tool, Xilinx Vivado, Xilinx ISE, Kiel Microvision, MS office Soft Skills

Languages English - Professional Fluency

Hindi - Basic Fluency

Odia - Mother Tongue

Soft Skills Ability to create a friendly environment and build up trust. Good Communication Skills

Ability to work under high presssure situation with patience Extra Curricular Activities

PLUGGED-IN Circuit Designer, 2016 - May 2019

Plugged-In is a Electrical and Electronics Club of NIT Rourkela, in which I have partici- pated in Smart Inverter and Home automation project ROBOSUMO Event Coordinator and Organizer, Nov 2017 A manual or automated BOT fight event organized at INNOVISION(NITR Techfest) which was coordinated by me and organised by PLUGGED-IN. Scholarships and Certificates

2017 Embedded event organized by IIT Kanpur - Second postion 2017 Led flasher and classifier circuit for Diesel Locomotives Interests and Activities

Academic Interests: Digital Electronics, Digital Design using Verilog HDL and Tanner Tool, Embedded Systems, Computer System Architecuture

Non-Academic Interests: Playing Football,Sketching,Reading Articles related to recent technological advancement Activities: Small attempts in making projects like automated flying drone, or a robotic arm, Reading Projects Thesis Hobbies: Chess, Football, Travelling, Cooking, Sketching, DIY projects

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