Nardev Mor

ac9o0a@r.postjobfree.com 916-***-**** Sacramento, California, United States

EDUCATION

**/**** – 05/2019

Master of Science In Electrical & Electronics

Engineering

California State University, Sacramento

Sacramento,CA, USA

08/2012 – 06/2016

Bachelor Of Technology in Electronics &

Communications Engineering

Kurukshetra University

Kurukshetra,HR,India

PROJECTS

Design of a High Speed Latching Comparator PSPICE

(09/2018 – 11/2018)

Designed a fully differential high-speed latching comparator in 0.18 μm technology node

Verilog Modelling and Generating Automated Test Vectors for Multiple Designs Verilog,Synopsys VCS, PERL

(09/2018 – 11/2018)

Modeled a 4-bit Adder, 4-Bit ALU, memory module & BCD counter using Verilog

• Generated automated test vectors using PERL • Verified designs by comparison of the expected results with actual results. Design, Verification & Synthesis of a Parallel to Serial Interface System Verilog, Synopsys VCS, Design Compiler

(02/2018 – 05/2018)

Designed and modeled a parallel to serial interface that can receive packet data, appending start & end delimiters and transmitting it through a serial output. Used an Asynchronous FIFO as the memory element. • Verified the design using an automated test-bench, also performed directed testing to test specific fault conditions. • Achieved a total code coverage of 90% Investigation of Non-Idealities of a 6-Bit Dual Slope Analog to Digital Converter using a Behavioural Model (10/2017 – 11/2017) Conditions Analyzed for a 6-bit Dual Slope ADC: Operational Amplifier and Comparator Non-Idealities like low voltage gain, low bandwidth, input offset voltage and Input capacitance.

Design of an Operational Amplifier for a given set of specifications PSPICE (09/2017 – 10/2017)

Designed a telescopic operational amplifier in 0.18μm CMOS process & fine tuned its performance to achieve the desired performance Design, Simulation and Layout of an Arithematic Logic Unit Cadence Virtuoso (09/2017 – 11/2017)

Designed a 4-bit ALU with Adder/Subractor, Bidirectional Shifter, Multiplier and Divider using 0.18μm CMOS process for all basic building blocks. Design of an Operational Amplifier to meet a 3-Sigma input referred offset Voltage using Monte Carlo Analysis PSPICE

(03/2018 – 05/2018)

Design of a 2-Stage Operational Amplifier to meet following Specifications: 1. Input referred Vos < 3mV (3 sigma) 2. Unity gain bandwidth as large as is possible 3. Phase margin at unity gain of at least 70degrees 4. DC open loop gain >70dB

SKILLS

System Verilog Verilog ALTIUM PYTHON

Synopsys design vision Synopsys prime time

RTL Design & Verification Static Timing Analysis

Cadence Virtuoso Pspice Oracle CAD

COMSOL Multiphysics MATLAB & SIMULINK MULTISIM

XILINX LINUX TCL Design for Testability C/C++

PCB Design Analog Circuit Design Phase Locked loops ADC DAC Comparators

WORK EXPERIENCE

PCB Design Engineer at Netmax Technologies pvt Ltd

(06/2016 – 07/2017)

Designed Electronic circuits using CAD tools..

RESEARCH PAPERS

ANALYSIS OF 3D MEMS ACCELEROMETER in American

International Journal of Research in Science, Technology,Engineering & Mathematics ISSN 2328-3580 March- May 2016 issue 14 Volume 1

MEMS CAPACITIVE ACCELEROMETER- DESIGN & SIMULATION in American International Journal of Research in Science, Technology,Engineering & Mathematics ISSN 2328-3580 September – November 2016 issue 16 Volume 1

COURSES

Analog and Mixed Signal Integrated Circuit Design

Digital Integrated Circuit Design.

Micro-Computer System Design I. Key Mixed-Signal IC Blocks Advanced Semiconductor Devices.

Computational Methods and Applications.

Hierarchical Digital Design Methodology.

Advanced Timing Analysis. Microcomputer System Design II Advanced VLSI Design-For-Test

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