Engineer Design

Anandhan K N

E-Mail: ************@*****.**.**; Contact: 990-***-****

Address: **, *** * **** ****, Punyabhoomi lyt, Kalkere, Horamavu post, Bangalore 560043,

Seeking challenging assignments in Board Layout Designing and Project Management with an organisation of high repute

Professional Preface

•An astute Professional with over 19 years of comprehensive experience in Board Layout Designing and Project Management.

•Recently Associated with Vadatech India Pvt Ltd Bangalore as Lead Engineer

•Adept at managing Design Engineering operations involving design & development, developing detailed drawing for fabrication, co-ordination with internal departments.

•Strong ability to create / read / interpret engineering drawings with proficiency in designing & developing new products in conformance to pre-defined technical specifications.

•Proficiency in development of vendors and analytical assessment, to strengthen effectiveness.

•Possess excellent communication & negotiation skills with strong organisational & team building abilities.

Areas of Expertise

Technical

ECAD Software:-

PCB layout : ALLEGRO 13.x to 16.x, CADSTAR, Altium 16x to 18x & PADS 2005

Schematic : ORCAD, CADENCE (CHDL) & Altium 18x

CAM Tools:-

•VALOR, GC PREVIEW, CAMTASTIC and VIEW MATE.

Functional

•Analysing and producing the technical requirements and specifications.

•Suggesting design modifications based on client requirements.

•Monitoring product quality & impact of design modifications on product features.

•Having project management experience in software installation, software testing, user acceptance testing and release to production. Contributing in project evaluation, conception and completion.

•Coordinating projects for the set up standards with accountability for strategic utilisation & deployment of Available resources to achieve organisational objectives.

•Focussing on cost reduction, time cycle reduction, improvement of process variables and enhancement of process conditions. Ensuring completion of all project activities within the time & cost parameters.

•Providing design support to new product introduction of various products.

•Getting approvals for prototype, making necessary modifications and releasing for production.

•Researching, developing, testing and implementing helpful programs to automate redundant tasks along with seeking better ways to reduce time of development.

•Understanding overall operations for improvement of existing products with thrust on reducing product cost and based on market trends / requirements.

Employment Scan

TENURE ORGANISATION

2018 – 2019 Vadatech India Pvt Ltd, Bangalore

Lead Engineer.

2014 – 2017 Brocade Communications Inc., Bangalore

Sr.Pcb Layout Engineer.

2008 - 2013 Cisco Systems Inc., Bangalore

Engineer - CAD Engineering

2004-2007 Enventure Technologies, Bangalore

Sr.Design Engineer & Team Leader

1999-2003 Kamal Elektronix, Bangalore

PCB Design Engineer

Accountabilities at Vadatech.

Designing of AMC, VPX, FMC, MRT board designs from Start to Fabout by working with cross functional Team of EE, ME, SI,POWER & RF engineer’s),

Accountabilities at Brocade Communications

•Designing multiple HDI design boards of projects from start to Fabout levels by working with cross-functional groups like (EE, ME, SI, POWER, NPI & SBE’s).

•Working:-

•With Internal & Global Engineering teams by collaboration through different Geographical Time zones.

•Providing ideas & guidance across CAD team on Automation programs to reduce design cycle time frame.

Awards

•Recognition as the first eCAD person to work from India on collaboration model with US team.

Accountabilities at Cisco Systems

•Designing multiple HDI design boards of projects from start to Fabout levels by working with cross-functional groups like (PM, EE, ME, SI, POWER, EMI, SAFETY, EPE, & CM’s).

•Working:-

•With Internal & Global Engineering teams by collaboration through different Geographical Time zones.

•On Value Engineering projects to reduce product cost.

•On Lead-free conversion boards.

•Executing projects by Partnering with outsourcing vendors internal & outside India. Guided the engineers to meet cisco design requirements & to meet Deliverables on time with zero defects designs.

•Providing ideas & guidance on Automation programs to reduce design cycle time frame.

•Conducting internal trainings to the contract engineers on Cisco PCB Design process, rules & methods to be followed & helped them during project execution.

Awards

•Recognition as the first person to work from India on collaboration model with US team.

•Board layer reduction for a high speed line card from 24 to 20 layers to reduce the cost. Worked closely with EE’s, EPE, Manufacturing team & SI engineers on stackup modification to meet the goal & same has been delivered within the schedule dates.

•Received multiple Cisco Achievement Program awards for delivering the designs on time, supporting the programs.

Accountabilities at Enventure Technologies

•Handled design team of six members working for US & Other Geographical Clients on Dedicated & project specific delivery models.

•Successfully developed the Library team for US clients & supports done on different geographical time zones. Followed the IPC standard IPC-7351 guidelines for the footprint development.

•Involved in the preparation and maintenance of standard libraries for PCB design.

•Involved in the preparation of ISO 9001:2000 standards for PCB Group.

•Designed feasibility; prepare time estimation, Scheduling and monitoring of project status.

•Liaised with client liaison, Quality checks of board layout and Training.

•Represented from Ecad in the Business and Management Meetings of the Company & provided trainings to the Business group on PCB layout Technical specifications.

Awards

•Employee of the year 2004.

Accountabilities at Kamal Elektronix:

•Schematic Drafting and Footprint creations and Board layout for Public, Govt & Telecom Domains.not

Board Design Knowledge

•Designed Multilayer PCB’s up to 32 layers using through-hole, Blind & Buried via, vippo & Backdrill Technologies with 3 mil Trace & 8 mil vias.

•Thorough knowledge and understanding of High Speed concepts including single ended and differential pair signals routings and worked on designs supporting Data rate up to 10 Gb/s with different technologies.

•Leverage the understanding of Manufacturing limits & standards to reduce the PCB cost.

Design Technologies Worked

•Designed different types of PCBs (e.g. Add on cards, Telephone boards, Networking boards, Power supply cards, Analog & Digital cards, RF boards, Server Mother Boards, etc.) from Single sided to multilayer boards having various component packages like through hole, press fit, SMD, PLCC, PGA & BGA (1mm 1.27 mm& 0.8mm pin Pitch) and Micro BGA (0.6mm & 0.5mm Pitch) using through hole, blind & buried via, micro via. Some of the high speed busses worked on are: Hyper Transport 3 (HT3), Front Side Bus (FSB) DDR2, DDR3 memory, PCI, PCI express (PCI-E) and High Speed data busses up to 10Gbps.

Scholastics

Diploma in Instrumentation Technology

M.E.I Polytechnic, Bangalore, Karnataka in 1995.

Personal Dossier

Date of Birth : 31 / 12 / 1976

Linguistic Abilities : English, Tamil, Kannada, Hindi.

Kindly refer attached annexure for project details

ANNEXURE

Projects Executed

Project1 :

Description : This is for SLX platform using ASIC of Qumran MX+ (BCM8838X) is 900Gbps Traffic Manager (TM) and 835Mpps Packet Processor (PP) with an integrated fabric interface and network interface.

Design with Key Interfaces of PCIe x2 Gen2,External Packet buffering: 8 channels of 32bit GDDR5 Network interface (NIF/NIFe): 24 lanes of 10/1 Gbps SerDes and 48 lanes of 25Gbps SerDes. STATS FPGA interface: Two CAUI-4. KBP- 16 lane Interlaken over fabric, External Clocks with speed of 156, 100,25MHz

Challenges:, Most complex board with 10k Parts with 30k connections, which is delivered in Eight week time schedule from placement to Fabout completion to be done. It has more than 200 power rail which need to implement in six power layers, followed pll power which had tight tolerance to clear sim results.

Project2 :

Description : Tyr is a platform supporting FOS, Fiber channel Switching based on Condor 4+ ASIC supporting U-ports functionality and higher scalability that is packaged in a 2RU rack-mount footprint. It has One MB, One DC support the 96X32G + 8X128G I/O. The MB is designed around T1042 Processor and it includes 3 Condor 4+ ASICs to support 48x32G/48x10G SFP ports + 4x128G/4x40GE QSFP ports. The DC also includes 3 Condor 4+ ASICs to support the remaining 48x32G/48x10G SFP ports + 4x128G/4x40GE QSFP ports. Design also consists of Management Ehternet, i2c, RTC, UART, DDR4, Pcie, Voltage monitoring Interfaces & using Power modules for power inputs to devices.

Project3 : .

Description : This is the first 40Gbps fixed port line card. This is a 20 layer PCB with many high speed data interfaces (Interlaken @6.5Gbps, PCIe, XAUI, ESI links etc) and high speed memory interfaces (serial TCAM, DDR3, RLDRAM). The key challenge was to accommodate all the routing within 20 layers to keep the cost low, at the same time meet the technical requirements.

Project4 :

Description : ASR 9001 is a compact, high-capacity, provider-edge router in (2RU) form factor. Which support 1g, 10g & 40 Gigabit Ethernet modular port Adapters. The design interfaces includes P4040 multi core processor from Freescale for both the RP and LC CPU complexes, CPU is connected to 2 RDIMM Slots and each slot can support upto maximum memory density of 8GB. Supports BITS,IEEE1588 timing interfaces. Design challenges are to deliver all MB, DC, power & Fan cards at same time. Interacted with cross functional Engineer’s & Delivered in 2.5 months.

Project5 :

Description : This is a line card uses the Cisco Packet Processor consists of Two Main ASICS which support Interfaces like RLDRAM up to 8 numbers, QDR-II SRAM TCAM4, ICB & CSR bus, 400MHz SPI4.2 point to point bus between multiple chips, RLDRAM driving the clocks to 400 MHz Frequency & runs at 333 MHz speed. 500MHz DDR2 CPU memory, 666MHz DDR ASIC to ASIC differential signal parallel bus & Timing critical 125MHz fabric request grant interface to backplane. The board is very dense in terms of component placement and has daughter card and mother board to optimize on the space and ease routing. The power dissipation is 400W total which makes component placement much critical. Worked with all Ecad Team Designers & collaboration with US & Wipro Ecad team members to complete the Design schedule.

Project6 :

Description : Intel X86 based Route Processor card, Layout consists of high speed (48 bit 500MHz DDR Elastic IO interface, HSTL) including connector pin optimization across BGA to BGA, Gen 2 PCIe interface across board to board connector including custom breakout pattern, other interfaces such as XAUI nets.

Project7 :

Description : Cisco owned Two Cisco packet processor ASICs, Some of the interface include Freescale P2020 1.0GHz dual core as control processor. 64-bit (+ECC) DDR3 memory at 400 MHz, 8MByte Boot Rom, 2GByte SD-Flash for NVRAM storage. Console RS232 port 1 Management Ethernet (10/100/1000) port), USB-console port Flash mass storage port, 5V power). BITS clock, TOD RS422 & PPS RS422.Composite clock inputs (64 kHz, 64 kHz + 8 kHz, 64kHz + 8kHz+ 400Hz). This Design challenges was to get good Thermal flow for Two Asics chip which are attached with Heatsinks & to accommodate all the interfaces in the given form factor of 22 layer stackup & this is done in the 20days time frame.

Project8 : Pentium III- Mother Board (18 layers).

Description : Higher End PC using Via chipset. This board was designed with different via types of through hole, Blind & buried. The board layout was very tight & optimized the circuit to fit the parts in the given board size.

Project9 : CRB 48+4 port for Telecommunication.

Description : Designed for Intel &this was the highest number of ports designed.

Project10 : Digital audio player (MP3) board for Telecommunication.

Description : Converted a 4 layer size 90.00 mm X 135.00 mm card to a 2 Layer size 57.0 mm X 81.0.This card worked without any problem during first bring up. The reception of this card was excellent & noise free.

Project 11:

The VPXxxx is a FPGA Carrier (VITA 46) with an FMC (VITA 57) interface. The unit has an on-board, re-configurable FPGA which interfaces directly to the FMC DP0-9 and all FMC LA/HA/HB pairs. The FPGA has interface to two DDR3 memory channels (64-bit wide and 16-bit wide) for a total of 2.5 GB. This allows for large buffer sizes to be stored during processing as well as for queuing the data to the host. The module supports dual GbE and, dependent on FPGA code loaded, PCIe up to Gen3 (dual x4 or x8 lane), or dual SRIO, 10GbE or 40GbE on P1. The VPXxxx provides health management through a dedicated management processor (including temp, voltage, FRU info, etc.). The unit is available in a range of temperature and shock/vib specifications per ANSI/VITA 47, up to V3 and OS2.

Project 12:

The FMCX is a FPGA Mezzanine Card (FMC) per VITA 57.1 standard, offering small footprint and low power dual fully featured wideband Rx/Tx channels. The FMC232 combines RF front end, frequency synthesizers for Rx and for Tx, mixed signal baseband section and flexible digital interface to host processor through the LPC connector. The FMC232 operates within the 70 MHz to 6.0 GHz frequency range, covering most licensed and unlicensed bands, and provides an instantaneous bandwidth programmable from 200 KHz to 56 MHz. Utilizing an AD9361 RF transceiver, the chip offers high performance noise figure and linearity. Each Receiver (RX) subsystem includes independent Automatic Gain Control (AGC), quadrature correction, dc offset correction, and digital filtering.

Project 13:

The MRTx is a Rear Transition Module (RTM) for VadaTech’s AMCX. The MRTX accepts a mezzanine card (sold separately) to provide the ADC, DAC and Clock I/Os.The MRTX provides three quad channel ADCs (AD9653) on board to provide a total of 12 channels ADC 16-bit @ 125 MSPS. The ADC accept input voltage of +/–1V DC coupled, 100 Ohm load. There are also dual DAC outputs with routing to the AMCX where the DAC ICs reside. The ADCs, DAC and Clocks signals to the mezzanine are provided through five 20-pin ZIF connectors on-board the MRTXXX

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