Mask Layout Designer
Resume:
Robert A. Fosket
Career Summary ** years of professional work including Full Custom, Standard Cell, Pad and Concept designs. Designs have spanned in digital logic in both CMOS and bipolar processes, mixed signal and analog in CMOS / Bi-CMOS designs. I love to learn and adapt to new and challenging processes and methodologies. I get along well with others, while also working efficiently on my own. I am seeking a position where I can excel while giving my best to my employer. I'm a dedicated individual who has an ambition to produce the best IC designs possible.
Experience
GlobalFoundries 2016-2018 Lago Vista, TX
• Senior R&D Lead Mask Layout Design Consultant.
• Off-site contract working from my home office.
• 2.7 years experience High Speed Analog Mixed Signal design.
• Designed 100+ Layout + Schematic’s for varying voltage and type
Ring Oscillator with Divider DUT macro’s.
• Designed 8 Self-Heating Sensor DUT macro’s, RX DUT Pad array
Macro, 2 Analog device defective detector macro’s.
• Designed 4 ReRm Chain DUT macro’s, 4 VPNP Mismatch DUT macro’s,
1200 Pad PDEN environment test blocks.
• Designed 12 Kelvin & Sensor probe Ring Oscillator DUT macro’s.
• Designed 7 Reliability Stress DUT macro’s for Electro
migration, Thermal cycle, Stress migration and TDDB.
• Experience in submicron design GlobalFoundries 7nm FinFet 6T/9T
• Experience in submicron design GlobalFoundries 12FDX.
• Experience in submicron design GlobalFoundries 14nm FinFet.
• Experience in submicron design GlobalFoundries 22FDX.
• Experience in submicron design GlobalFoundries 45RF.
• Experience using Cadence Virtuoso XL tools.
• Experience using Caliber for FABDRC/DRC/TSC/MSC/PCC/LVS
verification.
Avnera 2015-2016 Lago Vista, TX
• Senior RFIC Mask Layout Design Consultant.
• Off-site contract working from my home office.
• 5 months experience RF High Speed Analog Mixed Signal design.
• Full custom designed Analog Switching Regulator
(ldo,dac,bias,comp,core,switches,lshift,controller).
• Full custom designed DVM_top
(3 mux units,2 biasgen’s,ldo,clkgen,diag,comp,antialias_filter).
• Full custom designed SAR ADC Comparator
(comparator’s,preamp,dual bias,comp_ota,switches).
• Experience using Cadence Virtuoso XL tools.
• Experience using Caliber verification.
• Experience in submicron design TSMC 65nm.
Broadcom 2014-2015 Irvine, CA / San Diego, CA
• Senior RFIC Mask Layout Design Consultant.
• Groups I have worked for Bluetooth, C.E. Optical, Radio WiFi.
• 1.8 years experience RF High Speed Analog Mixed Signal design.
• Designed multiple units WLAN Dual-Band Transmitter, afedivider,
logen, tx_bias_top, op-amp’s, mixer’s, power detector’s, current
mirror, adc, dac, lna, pll, tx(trans), rx(rec), bias’s, charge
pump’s, vco, clkgen’s, tuner, slicer, Serdes, SoC, top level
placement and routes to tapeout along with major ESD fixes.
• 1.8 years experience using OA 6.1.5 Cadence Virtuoso XL tools.
• 1.8 years experience using Caliber verification.
• Experience in submicron design JAZZ 18nm Bi-CMOS SiGe.
• Experience in submicron design TSMC 28nm.
• Experience in submicron design TSMC 40lp.
Intel 2012-2013 Folsom, CA
• Senior RFIC Mask Layout Design Consultant.
• 1.5 years experience High Speed Analog Mixed Signal design.
• Designed multiple units on two 3D NAND chips some specific
area’s amps, comparators, pre-amp, cores, high density memory
modules, sense amps, clocks, srams, termo, level shifters, top
level data paths, periphery power grid, standard cell library’s.
• 1.5 years experience using OA 6.1.5 Cadence Virtuoso XL tools.
• 1.5 years experience using Caliber verification.
• Experience in submicron design Micron 18nm.
Qualcomm 2005-2011 Austin, TX / Raleigh, NC /
San Diego, CA
• Senior IC Mask Layout Design Consultant.
• 6.5 years experience CMOS full custom Mixed Signal design.
• Optimize layout of highly distributed and wire dominated
macro's to achieve specified timing with optimal area free of
hostile capacitive coupling with a solid understanding of DFM,LDP
and ERC issues.
• Designed multiple macro units some specific area's R&D
analglyph test project, noise, L2, data, tag, sram, drom, booth
recoding multiplexers, compressors, cache, pulse latches, clock
driver circuits for high performance clock trees.
• 6.5 years experience using latest Cadence Virtuoso XL tools.
• 6.5 years experience using Caliber verification and Redhawk
tools.
• Experience in digital, mixed signal, analog routing, soc, high
and low voltage.
• Experience in submicron design TSMC 90nm, 65nm, 45nm, 28nm.
IBM and Intel 1999-2005 Austin, TX / Hudson, MA / Chandler, AZ
/ Raleigh, NC
• Senior IC Mask Layout Design Consultant.
• 6.5 years experience CMOS full custom VLSI design.
• Created floor plans for timing critical macro's for IBM's
Gigahertz Server Microprocessor's.
• Worked on multiple microprocessor units up to eight metal some
specific area's camram, utlb, dram, src, ldst, bit, sram, L2,
dreg, data, rom, clocking circuits, multiplier, muxes, shifters,
pll, adc, dac.
• 5.0 years experience using the latest Cadence tools.
• 1.5 years experience using Intel's DLS, PLE, GENESYS and GALAXY
tools.
• 6.5 years experience using a multiple number of DRC, LVS,
Methodology and Yield verification tools.
• Experience in digital, analog, mixed signal, high and low
voltage designs.
• Trained in ASIC PD with Chipbench and PDS tools.
• Experience in device generated placement tools.
• Experience in submicron design .18u,90nm,65nm,45nm.
• Extensive background in IO development.
AMD, Motorola, IMS, Crystal 1992-1998 Austin, Texas
• Senior IC Mask Layout Design Consultant.
• 6.5 years experience CMOS full custom design.
• 6.5 years experience using Dracula DRC and LVS verification.
• 2.5 years experience using Cadence Opus.
• 2.5 years experience using DIVA verification.
• 1.5 years experience using MENTOR graphics.
• Worked on multiple five metal microprocessor's some specific
area's pll, dll, dpath, dcache, timer, cpu, ldst, dram, sram,
rom, comparator, amplifier, transceiver.
• Responsible for half of the layout and plan development for
the entire AMD's MIDI chip.
• Developed .5, .35 and .25 standard cell library for AMD, IMS
and MOTOROLA.
• Extensive background in IO PAD development.
• Experience in digital, analog, mixed signal, memory, high and
low voltage designs.
Motorola 1990-1992 Austin, Texas
• Staff Mask Layout Designer.
• Created macro's for 16bit and 32bit microprocessors.
Education
1988-1990 A.C.C. Austin, Texas
• Technical Degree in IC Layout Design
1981-1983 W.M.U. Kalamazoo, Michigan
• Associates Degree in Business
Contact
*******@*****.***
References
https://www.linkedin.com/pub/robert-fosket/3/750/909
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