Engineer Design

JIMMY LEW STORIE

ANALOG MIXED SIGNAL LAYOUT ENGINEER

**** ***** **** ****** #** Mesa, AZ 85205 480-***-****

*****.******@*****.***

PROFESSIONAL EXPERIENCE

Oct.2018 -Mar.2019 R.F Layout Engineer Skyworks INC

Custom Blue Tooth Group Beaverton, Oregon

·Worked on a 40nm TSMC

·Layout was done using Cadence Virtuoso – XL

·Verification done using Mentor Calibre

Oct. 2017 – Jan. 2018 Mask Designer 3 INTEL Contractor

Intel Custom Foundary Group Chandler, Arizona

·Building Templates & Test Structures in 10nm, 12nm, 22nm

·Layout was done using Cadence Virtuoso – XL version 6.

·Verification done using Synopsys- Integrated Circuit Validator, Mentor Calibre

·Physical Verification System used - Cadence

May 2017 – Aug. 2017 Analog Layout Engineer INTEL Contractor

High Voltage Group Hampton, New Jersey

·Worked on a 130nm DC DC POWER SoC

·Layout was done using Cadence Virtuoso – XL.

·DRC completed with Mentor Calibre

·LVS completed with Cadence Assura

Nov. 2016 – Feb. 2017 Analog Layout Engineer On Semiconductor Contractor

Image Sensor Group Corvallis, Oregon

·Worked on an Image Sensor Chip

·Executed layout from Aptina 250nm to TSMC 65nm process

·Main responsibility included Pixel Row Decoding

·Layout completed with Cadence Virtuoso – XL.

·Verification performed using Mentor Calibre

Mar. 2016 – Oct. 2016 RFIC Layout Engineer Soft Bank Group Contractor

RFIC Analog Group Deerfield Beach, FL

·Worked on a Bluetooth / 802.11 radio chip

·Executed layout in both UMC & TSMC 55 & 40 nm process

·Main responsibility was converting both 55nm chips to 40 nm version of the chip

·Major portion of chip work was Sigma Delta ADC and PLL

·Layout was done using Cadence Virtuoso – XL.

·Verification was performed using Mentor Calibre

Jun. 2015 – Jan. 2016 RFIC Layout Engineer Keysight Technologies (formerly Agilent Technologies) Contractor Mixed Signal Electronics Dept. Santa Clara, CA

·Worked on a High Speed Multi – Bit, Multi – Channel DAC, ADC, PLL, CMU, VCO, LVDS, Rx,Tx

·Worked in ST FDSOI 28 nm process

·Layout is being done using Cadence Virtuoso – XL

·Verification performed using Mentor Calibre

Feb. 2015 - May 2015 RFIC Layout Engineer Arm RFIC Analog Group Contractor Deerfield Beach, FL

·Executed layout in the UMC 55 nm process

·Worked on a Bluetooth / 802.11 radio chip

·Main responsibility was for converting TSMC 55nm to UMC 55nm version of the chip

·Layout was done using Cadence Virtuoso – XL.

·Verification was performed using Mentor Calibre

Jul. 2014 – Feb. 2015 Analog Mixed Signal Layout INTEL Contractor Hilisboro, OR

·Built an analog IP in Intel 14 nm FinFET

·Layout was done using Cadence Virtuoso – XL.

·Verification was performed using INTEL GPDS

May 2014 – Jul. 2014 RFIC Layout Designer Sunrise Micro Devices Contractor Deerfield, FL

·Executed layout in the TSMC 55 nm process

·Worked on Bluetooth / 802.11 radio chip

·Main responsibility was to work on a Sigma Delta ADC

·Layout was done using Cadence Virtuoso – XL.

·Verification was performed using Mentor Calibre

Sept. 2013 - Apr. 2014 High Voltage Analog Mixed Signal Layout Cirrus Logic Contractor Austin, TX

·Executed layout for Analog IP Library in Global Foundries 180nm ULL ISO High Voltage process

· Some blocks Worked on were: LDO, ADCR, COMPARATORS, BASE DRIVER, QPUMP, DAC, High Voltage Digital Logic Cells

·Layout was done using Cadence Virtuoso – XL

·Verification was performed using Mentor Calibre

Apr. 2013 - Sep.2013 High Voltage Analog Mixed Signal Layout Silicon Labs Contractor Austin, TX

·Performed layout on an ISOLATOR High Voltage Chip in VANGUARD 250 nm

·Some of the blocks Worked on were: DCDC, Pulse Width Controller, G.M Feedback Loop.

·Layout was being done using Cadence Virtuoso – XL.

·Verification was being performed using Mentor Calibre.

Oct. 2012 - Mar. 2013 Analog Mixed Signal Layout Qualcomm Contractor DAC Mixed Signal Group San Diego, CA

·Performed layout on a TxDac in TSMC 20nm

·Layout was being done using Cadence Virtuoso – XL.

·Verification was being performed using Mentor Calibre.

Mar. 2012 - Oct. 2012 High Voltage Analog Mixed Signal Layout Texas Instruments Consultant Precision Analog Group Dallas, TX

·Layout on a High Voltage DAC Test Chip with my portion being the DCDC section

·Layout was being done using Cadence Virtuoso – XL.

·Verification was being performed using Cadence Assura

Jun. 2010 - Dec. 2011 RFIC Layout Designer Agilent Technologies Santa Clara, CA

·Updated & made faster Serial Transceiver in ST 130nm triple-well dual-tub single poly BiCMOS process.

·For EMIR used Cadence “UltraSim Netlist-Based” tool.

·For DRC and LVS used Mentors Calibre

·Blocks completed were the following:

•.Input Amplifier, ESD, 7 bit DAC, Equalizer, phase detector, phase rotator, track-and-hold, eye sweep, charge-pump, squelch detector, UDLL, bandgap, Clock Multiplier Unit & several spiral inductors

·Worked on an ADC in ST CMOS065 (65nm) process

·Layout was being done using Cadence Virtuoso – XL

·For verification Mentors Calibre was used

Apr. 2010 - May 2010 RFIC Layout Designer PMC Sierra Contractor Allentown, PA

·Worked on a 2.5 GHz transmitter chip in TSMC (40nm) CMOS

·Top level routing by hand of 128 bit buss that passed LVS first time

·Assembled multiple large digital blocks

·Layout was done with Cadence Virtuoso-XL

·For verification Mentors Calibre was used

Dec. 2009 – Mar. 2010 RFIC Layout Designer Tagent CO. Contractor Mountain View, CA

·Worked on fully integrated, Antenna on Chip, RFID TAG

·Chip was created in IBM cmrf7sf/cmsoi7tf technology

·Layout was done with Cadence Virtuoso

·For verification Cadence PVS was used

May 2008 – Nov. 2009 RFIC Layout Designer Agilent Technologies Contractor Santa Clara, CA

·Worked on Layout of analog and custom digital circuits for very high speed ADC in BiCMOS (ST 130nm CMOS + 165 GHz bipolar, 7-layer metal, flip-chip)

·Layout of ECL logic gates and buffers, custom CMOS logic gates and buffers, low-jitter clock chains, DACs, high-power buffers, track-and-hold circuits, comparators, transmission-line wire channels. Work was completed from transistor level to the major-block level of the chip by using Cadence Virtuoso-XL and Mentor Calibre

·Worked closely with engineers to meet demanding requirements for low capacitance, good matching, electro migration, noise suppression and isolation, supply drops, density and global layout fit

Jan. 2008 – Apr. 2008 High Voltage Analog Mixed Signal Layout Akros Silicon Contractor Folsom, CA

·Worked as a Mask Designer on a POE (Power Over Ethernet) Chip.

·Layout was done using Chartered 180nm 20v.

·Layout tool that was used was Mentors IC Station-SDL.

·For verification Mentors Calibre was used

Oct. 2007 - Dec. 2007 Mask Designer AMD Sunnyvale, CA Contractor

·Worked on a 32nm AMD/IBM SOI test chip.

·Layout was done using Mentors IC Station-SDL

May 2006 - Oct. 2007 RFIC Layout Designer Agilent Technologies Contractor Santa Clara, CA

·Facilitated completion on layout of a Serial Transceiver in ST 130nm triple-well dual tub single poly BiCMOS process

·Layout completion of Input Pad including ESD, Input Amplifier, Equalizer, Squelch Detector, Eye Sweep, Fault Sensor, and Phase Detector and Performed place and route for digital interface using Cadence CCAR

·Layout was done using Cadence Virtuoso-XL

·For verification Mentors Calibre was used

Jul. 2005 - May 2006 High Voltage Analog Mixed Signal Layout Netlogic Microsystems Contractor Mountain View, CA

·Floor Planning of Power Rail Tiles on a TCAM chip in TSMC 90nm Deep N-well Process

·Layout completion of Memory layout of IP blocks.

·Layout of analog IP using 12v devices on Power Management Chip (12v/3v) in TSMC035HV

·Layout was done using Cadence Virtuoso-XL

·Edited and added to Hercules DRC run deck, as new layers came on line.

·Customized the Cadence Technology File for these new layers.

·For verification used Hercules

Aug. 2004 – Apr. 2005 RFIC Layout Engineer RFCO Semiconductor Los Gatos, CA (direct employee)

·Layout on a 5 GHz Wireless CDMA Multi-Band/Multi- Mode Receiver Radio Chip in IBM BiCMOS5HPE

·Layouts Included VCO, Mixer, Baseband, and LNA in IBM's BiCmos5hpe process

·Place and Router performed with Cadence Silicon Ensemble and Encounter

·Layout was done using Cadence Virtuoso-XL

·For verification Cadence's Assura and Diva was used

Jul. 2004 – Aug. 2004 RFIC Layout Designer Qual Core Logic Contractor Sunnyvale, CA

·Worked on a 2.5 GHz PLL in CM013.

·Layout was done using Cadence Virtuoso-XL

·Trained recent E.E. graduates on Cadence tools

·For verification Mentors Calibre was used

Sept. 2001 – Apr. 2004 RFIC Layout Designer Cypress Semiconductor San Jose, CA (direct employee)

·Facilitated completion on the following chips:

•.a Wireless USB (Mixed Signal) 2.4 GHz. Wireless System-on-a- Chip, 2.3 GHz Bluetooth Radio in BiCMOS, Bluetooth Baseband. Quad port 1 Gig Ram

·Place and Router performed with Cadence Silicon Ensemble.

·Layout was done using Cadence Virtuoso-XL

·For verification Assura and Calibre were used

Jul. 1999 – Sept. 2001 Design Engineer ATI Research Silicon Valley INC. San Clara, CA Worked as a Physical Design Engineer (direct employee)

·Facilitated completion on chips in TSMC .35um and .25 um South Bridge Chips

·Performed Place and Route on second generation “Raydieon” graphics accelerator chip

·Place and Router performed with Cadence Silicon Ensemble

·Layout was done using Cadence Virtuoso-XL

Mar. 1999 – Jun. 1999 Analog Mixed Signal Layout Designer Sandcraft / LSI Logic Contractor San Clara, CA

·Created Pad Cells with ESD and pad ring for LSI-LOGIC's Viper chip with a “Sandcraft SR1-GX” core

·Layout was done using Cadence Virtuoso-XL

·For verification Assura was used

Nov. 1998 – Feb. 1999 Analog Layout Engineer AMD Contractor Sunnyvale, CA

·Worked on analog CMOS Leaf & Block cells for the M11 & K11chips

·Used "Mentor IC Station" tools ICgraph, ICtrace, ICrules, Calibre

Jun. 1998 – Oct. 1998 Analog Layout Engineer Edge Semiconductor San Diego, CA

·Worked on "Clock Divider Chip" to completion using the Sony's P42 Bipolar Process.

·Chips were created using Cadence Virtuoso

·Completed verification by using Cadence Diva & for top-level verification used Mentor's Calibre

Nov. 1997 – May 1998 Unix System Administrator on Sun Solaris Motorola INC. Contractor Tempe, AZ

·Serviced hardware, software maintenance, upgrades on Sun Sparc stations and HP 750's

·Implemented a TCP/IP network for HP 750's

· Supported the "Image and Storage Division" and the "Wireless Products Group," by upgrading user machines from Sparcs to Ultra Sparcs

Mar. 1997 – Nov. 1997 Analog Layout Engineer INTEL Contractor Chandler, AZ

Built IP for an SROM

·Performed layout on an Analog CMOS Test chip

·Gained proficiency with Intel's internal tools such as Frolic, Zeus, and Design Level Synthesizer

·Gained proficiency on the AIX operating system using IBM RS6000 Workstation

Vendor Classes: Mentor Calibre, Mentor Systems Manager, Cadence Chip Assembler Router

College Courses: Basic Electronics, Electronic Math, Electronic Drafting, PCB Drafting, USC's UNIX System Administration

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