Design Designer

THOMAS IRVIN

Phone: 951-***-**** – cell 209-***-**** - Email: *******@********.***

EDUCATION

Intel University 1994 California State University, Fresno 1981 Bachelor of Science Degree in Economics

Humphrey’s School of Law: 1992 Bachelor of Science Degree

C.A.E. SKILLS

Cadence VXL 6.1.7 version Mentor Graphics Cell3 Layout

VI Editor Laker Unix

DAPR Cell layout Ledit/Tanner DLS(Genesys)

VERIFICATION TOOLS:

DRC LVS ISS Dracula Hercules Caliber RVE Diva Assura ICtrace

EXPERIENCE

SENIOR TEAM LEAD MASK DESIGNER

(responsible for: training (tool/CMOS), floor planning, tapeout, quality, debugging)

FinFet (10nm, 14nm) SOI (20nm, 28nm, 40nm)

SpaceX Irvine, Ca. (Cadence VXL 6.1.7) RF Analog team doing custom

Nov 17’ to Present analog full chip layout. SF Micro 28nm process RF-SOI process

Peregrine Semi: San Diego, Ca. (Cadence VXL 6.1.6) Senior Team Lead, R&D Analog

Oct 16’ to Nov 17’ team doing custom full chip layout. SOI custom designs, GF process

Broadcom: (2 tours) Irvine, Ca. (Cadence VXL 6.1.7) RF Analog team doing custom

Jan 14’ to Oct 16’ analog layout. 40 nm, SiGe custom designs and

Sept 12’ – Jan 13’ 28nm analog layout TSMC process

Global Foundries: (2 tours) Sunnyvale, Ca. (Cadence VXL6.1) Custom cell library design

Jan13’ - Jan 14’ 20nm, 14nm and 10nm Serdes design

Apr 09’ – May 11’ Custom test/analog structure layout

Qualcomm: San Diego, Ca. (Cadence VXL 6.1)

Oct 11’ – Sept12’ Part of RF Analog team doing custom analog, digital and block

level layout. 40-45nm TSMC process

Adesto Technologies: Sunnyvale, Ca. (Laker IC design)

April 11’ – Oct 11’ Custom memory chip design, layout including memory core

digital interface circuitry and analog read/write/ bias circuits.

Advanced Micro Devices: (6 tours) Sunnyvale, Ca. (Mentor Graphics/Cadence VXL)

June 07’- June 08’ Custom data path layout. Lead designer for the 45nm ‘address

generator’ including floor planning and layout of ‘adder-core’

‘imux’, ‘bypasXor’ and other interface circuitry.

Dec. 05’- Dec.06’ Lead layout designer for NVT team designing custom test

structures for their 65nm Mirror Bit technology process.

Nov. 03’- June 05’ Team leader for flash memory custom mixed signal and analog

layout. Analog layout of ‘sense amps’, ‘comparators’, ‘opamps’

‘dac_buffer’, ‘dac’ and ‘adc’ cells. Chip level routing/assembly.

Jan. 02’- Aug. 03’ Custom circuit layout for flash memory cells, ESD cell layout and

analog circuits. Analog layout of ‘sense amps’, ‘comparators’, ‘opamps’, ‘dac’ and ‘adc’ cells. Chip level routing and assembly.

Aug. 01’- Oct. 01’ Custom digital and analog circuit layout for flash memory cells.

Analog layout ‘sense amps’, ‘comparators’, ‘opamps’, ‘dacs’ ‘adcs’.

Jan. 01’- June 01’ Custom digital and analog circuit layout for flash memory cells.

Analog layout of ‘sense amps’ and ‘comparator’ cells.

Spansion LLC: (2 tours) Sunnyvale, Ca. (Cadence VXL/Mentor Graphics)

June 08’- Jan 09’ Lead contactor for the NVD (Non-Volatile Design)

team designing custom test structures, srams, 45nm process.

Apr. 07’- June 07’ Responsible for designing a custom drain/charge pump NVT team.

Rambus Inc: (2 tours) Los Altos, Ca. (Cadence)

Jan. 07’- Apr. 07’ Custom digital and analog circuit layout for ‘IBM’ process.

Analog layout of ‘sense amps’ and ‘comparators’.

Oct. 05’- Dec. 05’ Custom mixed signal and analog layout of ‘sense amps’, ‘dacs’

‘adcs’ and ‘opamps’.

National Semi-Conductor: (5 tours) Santa Clara, Ca. (Cadence)

June 05’- Oct. 05’ Custom chip layout of test structures for the ‘ATG’.

Aug. 00’- Oct. 00’ Custom chip layout of test structures for the ‘ATG’.

Sept. 99’- Mar. 00’ Chip layout of bipolar test structures/analog cell library cells.

Oct. 98’- Jan. 99’ Custom chip layout of test structures for the ‘ATG’.

Mar. 97’- Nov. 97’ Full chip layout for ‘ATG’ team. Custom test structures/library.

Sun Microsystems: Mountain View, Ca. (Cadence)

Aug. 03’- Nov. 03’ Custom digital layout and block level design rule updates.

Level One/Intel: Sacramento, Ca. (Cadence)

Nov. 01’- Jan. 02’ Lead for ESD structures, pad ring layout/top level assembly.

Transmeta: Santa Clara, Ca. (Cadence)

Oct. 01’-Nov. 01’ Custom digital/mixed signal. Block level assembly/debugging.

Tripath Technologies: Santa Clara, Ca. (Cadence)

June 01’- Aug. 01’ Custom analog layout of ‘imirror’, ‘fcasamp’, ‘bais’, ‘dac_buffer’, ‘icalbuf’, ‘dacs’, ‘adcs’ and ‘opamps’ cells.

Analog Devices Inc: Santa Clara, Ca. (Cadence)

Oct. 00’- Jan. 01’ Custom analog layout for integrated lcd grayscale generator.

Full chip layout including ‘dacs’, ‘dac_buffers’, ‘opamps’, ‘bias’.

Arcadia Design Systems: Santa Clara, Ca. (Cadence)

Mar. 00’- Aug. 00’ Custom ‘sram’ cell layout. Cell library through block level.

Hewlett Packard: Fort Collins, Co. (Cadence)

Jan. 99’- Sept. 99’ Custom digital chip layout, sram arrays, data path, cell library cells

C-Cube Technologies: San Jose, Ca. (Cadence)

Feb. 98’- June 98’ Custom ‘sram’ cell layout and ‘cell 3’ design and layout.

Cyrix Corp: Longmont, Co. (Cadence)

June 96’- Mar. 97’ Cell library design and layout, block level analysis/re-work.

Intel Corporation: Folsom, Ca. (DLS)

Feb. 95’- May 96’ Full custom block and chip level layout. CMOS instructor

for new team members and trainees

Contact this candidate