Santa Clara, CA, *****
Cell: 669-***-****; E-Mail: email@example.com
Versatile Process Engineer with extensive experience in semiconductor industry with strong technical, communication, writing, and ownership skills. Adept in Etch, Strip, Integration, and CMP processes. Recognized for solving complex issues, collaborating across teams and organizations, and simultaneously working on multiple projects in high-pressure situations.
DOE (Design of Experiments) Statistical Analysis (JMP, SPC, Excel) Analytical
Project Management Troubleshooter
Lam Research, Fremont, CA 2014 – Present
Etch Senior Process Engineer
Developed etch processes for customers to meet product specifications.
Fixed photoresist remaining issue and provided End-Point Detection solution to TSMC.
Developed new recipes for crust /residue removal to improve yield.
Hands-on experience with Lam etch tools with excellent plasma fundamentals.
Novellus Systems, San Jose, CA 2009 - 2013
Fabricated test structures (small features) using patterning/CD shrink approach, integrating different thin films.
Demonstrated CMP feasibility of WN/W + NiB films for success of novel integration scheme.
Developed new CMP processes, reducing Cost of Ownership (CoO).
Proposed e-test device structure, e-test method and integration scheme to characterize substrate loss in clean processes.
IBM, T. J. Watson Research Center, Yorktown Heights, NY 2006 - 2008
Developed new slurries for metal and barrier CMP, improving CMP performance.
Devised new CMP processes for defect reduction.
Sustained and maintained robust CMP processes.
Doctor of Philosophy (PHD), Chemistry, Clarkson University, New York, USA.
Master of Science (MS), Chemical Engineering, IIT, Delhi, India.
Bachelor of Science (BS), Chemical Engineering, Nagpur University, India.
Willing to relocate and travel.