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Electrical Engineering Design

Tampa, Florida, United States
May 13, 2019

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Rasagna Tummala



Master of Science, Electrical Engineering May 2019 University of South Florida, Tampa, FL GPA: 3.36

Related Courses: Introduction to VHDL, Rapid System Prototyping with FPGAs, Digital CMOS/ VLSI Design, Embedded systems, Digital Communication Systems, Wireless Networking and Internet Protocols, Statistical Inference, Robotics and Artificial Intelligence. Bachelor of Technology, Electronics & Communications Engineering May 2017 Jawaharlal Nehru Technological University, India GPA: 3.8

Related Courses: VHDL/VLSI Design, Embedded Systems, Digital and Linear Integrated Circuits, Digital Signal and Image Processing, Wireless Sensor Networks, Digital and Analog Communications. TECHNICAL SKILLS

Software Packages: C, Object Oriented Programming (C++, Java, Python) Hardware Description Languages: VHDL, Verilog, System Verilog, TCL Web Development: JavaScript, HTML

Tools: CAD, Auto CAD, CADENCE, HSPICE, MATLAB, MPLAB and MS Office Technological Proficiency: IoT, SQL, Telecommunications and Communication Protocols Operating Systems: Windows, Linux/ Unix

Certifications: Python Programming - Udemy


University of South Florida, Tampa, FL

Path Finding Robot Simulator - Java, A* Search algorithm Nov 2018

Developed an application that maps an area as a simulated robot explores the routes between the points, thus attempting to guide the robot to the goal point. PCB Implementation of Interfacing Bluetooth Module with PIC micro controller Dec 2018

Implemented a blue tooth (HC - 06) interface with the PIC micro controller (PIC18F45K50) making it wireless on a Printed Circuit Board(PCB) with a goal to transfer a serial data from an Android OS. Reduced TCP/IP Protocol Implementation on FPGA - CADENCE, X2go and Xilinx Apr 2018

Designed a simple reduced TCP/IP protocol stack in VHDL that can be used in a soft-core embedded system (SOPC system) on a Spartan-6 FPGA board using a Seven Segment Display to establish high speed link between remote terminals and host.

FPGA Implementation of AES Encryption and Decryption - Modelsim and Xilinx Mar 2018

Implemented the AES (Advanced Encryption Standard) algorithm, that can be used to protect the electronic data with regard to FPGA and the Very High Speed IC Hardware Description language


32 X 32 Bit Combinational Multiplier - CADENCE X2go Nov 2017

Designed a 32 X 32 Bit Combinational multiplier in CADENCE VHDL Simulator (X2go) in the Behavioral (at RTL level), Structural and high-level behavioral modules. 32-Bit Carry Look Ahead Adder - CADENCE X2go Oct 2017

Developed programs in CADENCE VHDL Simulator (X2go) for designing a 32-Bit Carry Look Ahead Adder and implemented the corresponding test benches. Design of a Custom Application Specific IC (N X N Array Multiplier) - CADENCE VIRTUOSO Dec 2017

Fabricated an N X N array multiplier (16 X 16bit Multiplier) in the specified chip area with in the pad frame provided in AMI 0.5um CMOS technology available through MOSIS. VLITS, JNTUK, Kakinada

Blood Vessel Segmentation of Retinal Images Using Gabor Wavelet - 2D Gabor Wavelet Jan 2017

Led a 4-member team to apply the process and knowledge of Digital Image Processing and Signal processing to diagnose diabetic retinopathy from images of retina using MATLAB. Implementation of Temperature Sensor for IoT Applications June 2016

Interfaced LM35 temperature sensor and Arduino along with its program using EMBEDDED C to display the temperature on a 16 2 LCD module.

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