T.S. SARAVANA KUMAR
VLSI design Engineer
Email ID: firstname.lastname@example.org
Blog ID: saravanavlsi.blogspot.com
Dynamic and career oriented engineering professional with hands on experience in designing VLSI integrated circuits and in developing embedded software. Looking for a responsible position as a VLSI design engineer with a view to utilize and enhance my skills and experience towards professional growth
Sasurie College of Engineering, Vijayamangalam
BE-Electronics & Communication Engineering
K.S.Rangasamy College of Technology, Tiruchengode.
Ashram Matriculation Higher Secondary School, Erode.
Periyar Centanary Memmorial Matriculation Higher Secondary School, Trichy.
Have completed an course on “Training Programme on IBM-MAINFRAME S/390 conducted at Software Training and Development Centre, Thiruvananthapuram” for a period of 3 months (26-08-2008 to 20-11-2008) in MVS, JCL, VSAM, VS COBOL II, DB 2 & CICS.
Completed a course on “COBOL Programming” for a period of 21 days (30-07-2008 to 21-08-2008).
AREAS OF INTEREST:
Advanced Digital System Design
Application Specific Integrated Circuits
Testing of VLSI circuits
VLSI Design Techniques
Operating Systems : Linux, Windows Family
VLSI Programming Languages : VHDL, Verilog HDL
Layout Tools : Tanner V7, Tanner V13, Microwind
VLSI Programming Tools : Xillinx 13.1, Xilinx 9.1
FPGA : Spartan-3E
KNOWLEDGE AND EXPERIENCE
Experienced in VHDL, Verilog, Xilinx Spartan FPGA programming.
Expertise in Digital Design
Proficient in RTL design, simulation and synthesis using Xilinx ISE, XST tools.
Experienced with Xilinx EDK Platform.
Knowledgeable in CMOS VLSI design, Verilog RTL coding.
1.UG PROJECT: VLSI Implementation of Viterbi Algorithm
2.PG PROJECT: Compact Carry Select Adder for DWT Applications
1.Design of Vedic Multiplier for Multiplier and Accumulator
2.Design of 8 Transistor Full Adders
3.Design of FIR Filter using Booth multiplier and SPST Adder
4.Design of IIR Filter using Wallace multiplier and SPST adder
5.Design of Smart Arithmetic and Logic Unit
6.VLSI Implementation of Karatsuba Multiplier
7.VLSI Implementation for CDMA NOC
8.Design of Vedic Multiplier using Reversible Logic gates
9.Design of Booth Multiplier using Optical Reversible gates
10.Design of Carry Skip Adder using Parallel Prefix matrix
11.Cryptography using Image Processing
12.Detection of Heart Disease using Matlab and Vlsi
Flexible and willingness to accept new challenges
Desire to learn and update emerging technologies
Ability to work as a group and individually
Excellent communication skills
Design and development of various HDL modules using Xilinx Spartan-3E FPGA board.
Xilinx FPGA board programming using ISE.
Design HDL modules using Xilinx IP cores.
Designing Projects using Schematic Entry in Xilinx Simulator.
Design logic level and physical layout verification using Microwind
Company Name: SPIRO Technologies
Designation: VLSI Trainer, Seminars in VLSI, Classes in Verilog & VHDL, Business Development Officer
Duration: 11 months
Company Name: MAHINDRA Next Wealth
Duration: 6 months
College: Sasurie College of Engineering
Duration: 6 months
Company Name: CRISP System India Private Limited.
Designation: VLSI Developer, Trainer, Seminars in VLSI, Classes in Verilog & VHDL, Tanner EDA, Microwind.
Duration: 1 Year
Company Name: Globaltek Research Organization
Designation: Development Engineer
Duration: 8 Month
Bagged second prize in mini-project “Automatic car parking” competition held at K.S.Rangasamy College of Technology, Tiruchengode.
Presented a paper in “Compact Carry Select Adder for DWT Applications” national and international conferences held at Institute of Road and Transport Technology and Sasurie College of Engineering, Vijamangalam.
Attended a workshop in “SYNOPSYS – VLSI Design Tool” in Kongu Engineering College, Perundurai.
Attended a workshop in “SOLID STATE MODELLING AND SIMULATION” in KPR Institute of Engineering and Technology, Arasur.
Attended a workshop in “Hands on Training in NS2” in Sasurie College of Engineering, Vijayamangalam.
Publication of the journal in International Journal of Advances in Engineering & Technology under the topic of “Area Minimization of Carry Select Adder using Boolean algebra”
Participated in various singing and oratorical competitions at school level.
Represented my school team in Volleyball competitions at Zonal level competitions.
Participate in cricket tournament in school level.
Name : T.S.SARAVANA KUMAR
Date of Birth : 12.04.1987
Age : 31
Blood group : B+
Mother’s Name : S. Kalarani (Late)
Father’s Name : T.S. Subramanian (Late)
Present address : 61/8, CSI colony, Sanarmedu, Erode-638 002, Tamil Nadu, INDIA
Permanent address : 61/8, CSI colony, Sanarmedu, Erode-638 002, Tamil Nadu, INDIA
Religion : Hindu
Nationality : Indian
Languages Known : Tamil, English
Hobbies : Reading books, Gardening, Playing Chess
I hereby declare that all the details furnished above are true and correct to the best of my knowledge.
(SARAVANA KUMAR T S)