Verification Engineer

J. JEFFERSON

**, ***** ******, ******** ******, Phone: +91-944*******

Kottur, Chennai - 600085 Email: **************@*****.***

CAREER OBJECTIVE:

Dedicated and hardworking aspirant towards achieving my goals that excel my work passion in the microelectronic industry. To be an integral part of a professional organisation, where I can exploit myself in the field of VLSI and to keep myself updated with the ever-growing cutting-edge technologies.

SUMMARY:

• Completed Master of Engineering Degree in VLSI Design at Anna University, College of Engineering Guindy and also various courses, workshops, publications and projects related to my career interest.

• Trained and experienced SoC chip design and verification engineer knowledgeable in developing testbench with SV/UVM for RTL design.

PROFESSIONAL EXPERIENCE:

MBit Wireless Pvt. Ltd. [Dec, 2016 – Present]

Designation: Development Engineer (3 years)

Role in the company:

Three years of experience in a Product based company for developing 4G/LTE Physical Layer Verification based on LTE 3GPP specification with 28nm technology.

Experience in UVM testbench development, generating testcases, register write and read-back test, issue recreation, post-processing with scripting and performing verification for various simulations. List of projects undertaken:

4G/LTE and LTE-A chip for Category-M and NarrowBand-IoT environment development

- UVM based testbench environment development for LTE 3GPP protocol in Physical Layer (36- series) specification by capturing the requirements, devising test plan and scenario population.

- Implementing subsystem for UL channel modules and SoC integration interacting with registers using AXI, DDR, ZTurbo and RFIC interface with SPI telegram using RBDP to air interface.

- Triggering extensive simulation with randomisation and extending the code and functional coverages to maximum.

- Qualifying the RTL for Non-CoSim verifications, PHY conformance and testcases defined by Global Certification Forum.

- SW write and read for Co-Sim, RTL to Netlist conversion and preparing SDF environment over the RTL design for final chip tape-out.

Recreation of issues observed in Lab validation and Field testing

- Analysing the logs and identifying root-cause of the problem.

- Implementing the workaround in testbench and resolving the issues.

Register scan and LUT read-back test verification

- Performing register write and read-back through AXI protocol with constraint randomisations.

- Verifying register models for storing and retrieving proper data in every address.

- Performing LUT data write and read-back through IO ports and AXI protocol.

- Verifying in Non-Cosim and Co-Sim environments for SW read and write.

Low power aware and master reset test verification

- Providing gated clock whenever the chip is in idle state.

- Switching off power for unwanted power domains when the chip is in flight mode.

- Recover from a state when RFIC throws an Interface Error to PHY.

- Resetting PHY and reinitiate simulation when the chip is unable to recover. Tools used for project:

Verification Language : System Verilog

Methodology : UVM

Verification tool : Synopsys VCS, Synopsys DVE

Scripting : Perl, Shell, Make

EDUCATION QUALIFICATION:

S.No. Course Name of Institution Board/University Year of passing

Percentage

1 M.E. VLSI Design College of Engineering

Guindy

Anna University 2016 7.94

(CGPA)

2 B.E. Electronics and

Communication

Prince Dr. K.Vasudevan

College of Engineering

Anna University 2014 7.6

(CGPA)

3 HSC AMM Matriculation Higher

Secondary School, Chennai.

State Board 2010 89.25 %

4 SSLC AMM Matriculation Higher

Secondary School, Chennai.

Matriculation 2008 83.6 %

COURSES COMPLETED:

• Certified course on VLSI and system implementation using Spartan 6 in NIELIT, Chennai.

• Online courses on System Verilog, UVM, Perl and Python.

AREAS OF INTEREST:

• ASIC and FPGA programming on RTL design and TB verification.

• Digital System Design, Electronic Design Automation and learning any new course.

INDUSTRIAL EXPOSTURE:

• Implementation on FPGA/ASIC in National Institute for Electronics and Information Technology.

• NFC based security using CPP protocol in Global Techno Solutions.

• In-plant training in BSNL and Chennai Port Trust.

• Industrial visit & Interactive seminar at TCS, Kochi.

ACADEMIC PROJECT DETAILS:

M.E. Project:

Title Data Compression using Self-Scaled CORDIC based DCT Architecture. Duration 10 months

Project Work Trigonometric computation using CORDIC rotators for reducing computation time and multiplier complexity.

Energy Compaction property of DCT images was used for image compression. Tools used Hardware: Zedboard Zynq-7000

Software: Xilinx ISE, Modelsim, Cadence, MATLAB

NIELIT Project:

Title Interfacing and verification of various protocols on FPGA and ASIC. Duration 2 months

Project Work Interfacing UART, PS2, RJ45, VGA, HDMI and Audio on Spartan 6.

Implementing Microblaze and Intelligent Property on FPGA. Tools used Hardware: Atlys, Anvyl, Stratix, Virtex, Kintex, Altera DE2. Software: Xilinx ISE, Vivado EDK and SDK, Quartus, Mentor Graphics. B.E. Project:

Title Self-updatable Conditional Privacy Protocol for preventing security threats in NFC Applications.

Duration 6 months

Project Work Algorithm for secure transaction by random number private key sharing technique.

Details taken from NFC transceivers without any third-party interference using Conditional Privacy security protocol.

Tools used Hardware: ARM LPC2148, Intel 8085/8086. Software: Keil uV, Proteus, TeraTerm.

TECHNICAL SKILLS:

HDL/HVL : Verilog, System Verilog

Methodologies : OVM, UVM

Scripting Languages : Perl, Shell, Make

EDA Tools : VCS, Xilinx, Synopsys-DVE

OS Platforms : Linux, Unix, Windows

WORKSHOPS:

• Mobile Broadband and Multimedia Communication in -The Institution of Engineers (India).

• Seminar on Cadence schematic to layout design flow in Anna University Chennai.

• Online webinars on UVM, MATLAB, System Verilog, Python etc.

PUBLICATIONS:

• “Self-Scaled CORDIC Rotators for Trigonometric Computation in DCT using Selective Iterations”, International Journal for VLSI Design and Communication System (IJVDCS) Vol.4 Iss.3.

• International Conference on Engineering, Technology and Science (ICETS).

• International Conference on Electrical, Electronics and Computer Engineering (ICEECE).

• National Conference on Computational Intelligence in Electrical and Electronics Engineering.

PERSONAL DETAILS:

• Communicate with spontaneity in Tamil and English.

• Playing cricket, tennis, sky watching and listening to songs are my hobbies.

DECLARATION:

I hereby declare that all the details furnished above are true to the best of my knowledge and belief. Chennai J. Jefferson

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