Engineering Project

SABARNO CHOWDHURY

ADDRESS : Block D, Flat No. – *R, S D Tower, Prafulla Kanan (West), Kolkata-700101 MOBILE NO. : 801-***-****

E-MAIL ID : ****************@*****.***

DOB : 18th July, 1993

ACADEMIC QUALIFICATIONS

Degree /

Certificate

Degree Discipline Institute Board /

University

Year of

Passing

Aggregate

% / CGPA

Post

Graduation

M. Tech.

VLSI Design

Indian Institute of

Engineering Science

and Technology,

Shibpur

- 2019 85.4%

Graduation

B. Tech.

Electronics &

Communication

Engineering

Institute of

Engineering and

Management,

Kolkata

MAKAUT 2016 9.09

12th

ISC

Science

St. Joans School,

Kolkata

CISCE 2012 93.5%

10th ISCE

General St. Joans School,

Kolkata

CISCE 2010 94.4%

WORK EXPERIENCE

Name of Institute /

Organization

Designation Duration

Institute of Engineering and

Management, Kolkata

Scientific Officer

(Laboratory Teacher)

1 year

(12th July, 2016 - 14th July, 2017)

TRAININGS UNDERTAKEN

Name of Institute /

Organization

Project Title

Duration

CETE Project based Training on

Microcontroller

4 weeks

BSNL Employability Enhancement Training

Programme (EETP)

72 hrs(Silver Course)

56 hrs(Gold Course)

56 hrs(Platinum Course)

PROJECTS

MTECH

Design of 14-bit Multi-channel Fully Differential SAR ADC for low frequency applications in SCL 180nm technology (SMDP Project funded by MHRD, GOI) Guides - Hafizur Rahaman and Subhajit Das

Abstract - The aforementioned ADC has been designed suitable for low frequency applications, such as in seismic sensors, biomedical applications and so on. All the individual components of the ADC have been carefully designed and tested in both schematic and layout views on Cadence Virtuoso® under SCL 180nm technology. In this MHRD project, my role was to develop the layouts of the designed analog and digital components. The digital standard cells layout has been made using 20 tracks with 1P4M process. In the analog domain, a FD OPAMP has been made using common centroid technique.

BTECH

Design of Self Clocking Logic Circuit Element & Some Basic Logic Functions using MOS based NDR and β-driven Threshold Element

Abstract - A new mathematical threshold logic gate block was proposed for the implementation of n-input Muller C element. A new circuit was also proposed which can implement various linearly separable logic functions in one circuit by varying circuit control voltage. The circuits were designed and then simulated using PSpice.

COMPUTER PROFICIENCY

C

C++

MATLAB

Xilinx ISE (Elementary)

Cadence Virtuoso (Spectre, Calibre)

PSpice (Elementary)

LANGUAGES KNOWN

BENGALI Mother tongue

ENGLISH Fluent

HINDI Fluent

GERMAN Elementary

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