Project Test

K SATISH CHOWDARY

Mobile: +91-949******* E-Mail :******.***********@*****.***

CAREER OBJECTIVE:

To utilize my technical knowledge and positive skills to be the part of the development of the organization and growth of the organization where in my growth will follow along with it.

SUMMARY:

0.6Years of experience in Digital Design and Verification.

Hands on experience in writing Test benches in System Verilog and UVM.

Hands on experience of enforcing Test Cases, SOC simulation and verification methodology.

Proficient in writing Test Plans, Test Scripts, Test Scenarios, Test Cases, and debugging RTL.

Strong Knowledge of OOP’s Concept.

Having experience in Industry-Level protocols PIPE (4.4.1, 5.1), SPI.

Good Analytical, troubleshooting organizational, communication, prioritization and problem- solving skills with ability to create and sustain high work tempo.

Ability to work effectively both independently and as a member of a team and good at team co- ordination and collaboration.

TECHNICAL SKILLS:

Operating System

WINDOWS, DOS, LINUX.

Programming Languages/ HDLs/ Methodologies

C, Core Java, Verilog, System Verilog, UVM.

IDEs and Tools

QuestaSim, ModelSim, Xilinx ISE, EDA Playground.

WORK EXPERIENCE:

Worked as ASIC Intern at Learnyzen (Venture of Asiczen Technologies) from 5th Mar, 2018.

EDUCATIONAL QUALIFICATION:

Completed Masters in Technology in 2018 from Sanketika Vidya Parishad College of Engineering with 65%.

Completed Bachelor in Technology in 2014 from Pydah college of Engineering with an aggregate of 60%.

Completed Intermediate in 2010 from Board of Secondary Education, Andhra Pradesh with an aggregate of 60%.

Completed Secondary School Certification in 2008 from Board of Secondary Education, Andhra Pradesh with an aggregate of 53.5%.

K SATISH CHOWDARY

Mobile: +91-949******* E-Mail:******.***********@*****.***

PROJECTS:

PIPE 5.1 UVC Development

This project involved creating a MAC and PHY UVC that supported PCIe, USB, SATA, Converged IO and Display Port functionalities and capable of supporting both PIPE-4.4.1 and PIPE-5.1 including PIPE assertions.

My Role:

Understanding the PIPE-5.1 specification

Understanding the existing UVC

Updating all the additional modes, rates, PCLK_Rates etc.

Verifying all the updates according to specification.

Developing new testcases for the same

Outlining coverage plans for functional level coverage.

PIPE UVC Development

This project involved creating a MAC and PHY UVC that supported PCIe, USB and SATA functionalities and was capable of driving the PIPE-4.3 and 4.4.1 interface including PIPE assertions.

My Role:

Understanding the PIPE specification

Understanding the existing UVC

Updated UVC to add USB related features

Updated PHY model to add USB related features

Writing testcases

SPI UVC Development

This project involved creating a UVC for serial peripheral interface with full duplex transmission. UVC involved both master and slave agents for simultaneous transmission and reception.

My Role:

Understood the SPI specification

Made feature list and verification plan

Created architecture document

Made test bench/ UVC components

Made testcases for testing

Worked on functional coverage

Dual port RAM Verification in UVM

This project involved two independent ports (reading and writing) and multiple writes/reads at same time. Involved no simultaneous read and write from same port.

My Role:

Understood the Dual port RAM specification

Created feature list and verification plan

Coded UVM test bench and testcases

Implemented functional coverage and scoreboard

Dual port RAM Verification in System Verilog

This project involved two independent ports (reading and writing) and multiple writes/reads at same time. Involved no simultaneous read and write from same port.

My Role:

Understood the Dual port RAM specification

Created feature list and verification plan

Coded SV test bench and testcases

Implemented functional coverage

Implemented scoreboard

4*1 Arbiter- Design and Verification in Verilog

This project involved 2 modes for order of servicing (Round robin with fixed priority and Round robin with starvation avoidance)

My Role:

Understood the 4*1 arbiter specification

Created feature list and verification plan

Designed the RTL

Coded test bench and wrote testcases in Verilog

Code coverage analysis

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