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Design Engineer

San Diego, CA
March 29, 2019

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CAREER OBJECTIVE: I am looking for a position as either an individual contributor or a lead/manage an ASIC/FPGA development team. I am interested in IC technology, flows and tools and prefer to stay hands on in any career moves. Currently I am looking to contribute in Physical Design.

STRENGTHS: Strong synthesis and Physical Design experience with complex multi hierarchical physical designs using multiple clock and power domains. Includes floorplaning, cell placement and routing, DFT, CTS. I have strong experience with Magma and Synopsys tools. Experience defining flows and bringing up flows. Design/SOC architecture, RTL Design / verification and full chip regression environments.

EXPERIENCE: Simulation experience with Synopsys/Cadence and Mentor tools. Synthesis experience with Synopsys DC, STA using PTSI, PnR experience with Synopsys ICC and Magma tools. I also experience with Questa CDC, Cadence Calibre and Apache Redhawk.

Design experience with embedded core such as ARM/ARC, Sonics/Arteris, AXI3/4, DDR3, NAND/NOR, Power Control, USB, GIGE, SERDES and GHz+ converters.

Professional Experience

Oct 2012 –present Carriercomm, San Diego, CA

Summary: ASIC Chip Lead

I led several teams of ASIC designers developing a Multicore SOC for Microwave backhaul applications.

I was responsible for Fullchip Integration, module level detailed design, Fullchip verification, synthesis, floorplan studies, package selection, post Silicon Validation specification, schedule maintenance etc. The IC went into pre-production on first pass silicon.

Lead engineer interacting with Silicon Vendor on various tapeouts. Worked with engineers on floorplanning, solving PnR issues, I/O placement, bump layout, package substrate design and closure and signoff of devices.

Led 4 offshore design teams designing a multiple CPU SOC with AXI interconnect. Teams varied from 4-6 engineers. Responsible for day to day direction/ guidance, prioritization and scheduling of tasks. Design included multiple DDR3-1600 interfaces, NAND interface, multiple 10.3Gpbs SERDES interfaces, Ethernet switch etc. The design had multiple high speed (GHz+ ADCs and DACs)

Led the FC synthesis, STA and Formal Equivalence activities. Established flows for the tools and participated at module and FC level to complete and close the designs.

2010 –Aug 2012 Microchip Technology, Chandler, AZ, USA

Summary: Leader of SOC development teams. Architect of SOC ICs, responsible for Design, Integration and Physical Implementation.

I Led 2 teams of ASIC designers developing 32 bit MIPs based SOCs. I was responsible for all aspects of the designs including planning and scheduling/resourcing. Worked on Roadmap definition (with marketing and architects), Die size estimation, pinout, package definition, feature lists, IP selections, process selections, tool selections, reviews, tapeouts. I was also responsible for hiring, team building, employee assessment/reviews for the team members that reported to me.

Did initial floorplans of devices to get an early look at design and bump-out so we could make recommendation to package substrate design team. Worked closely with package team on substrate design issues associated with high pinout devices.

Performed initial feasibility of a stacked die product where SOC and DDR memory were integrated into one package.

Worked the design hierarchy including the physical design hierarchy. Performed trial synthesis and ICC layouts to establish performance of systems in the pre design stage of a project.

Led evaluation and selection effort for selection of dynamic power analysis tools from Vendors such as Cadence and Apache.

Managed teams in Chandler and India, coordinated development activities between groups.

Managed the IP procurement team on selection processes and contract negotiations.

Coordinated the Program management team. Responsible for establishing program management flows and methodologies.

2008-2010 Silverbrook Research, Sydney, AUS -San Diego, CA

Summary: Lead Engineer for SOC development teams, Architect of SOC ICs, responsible for Design, Integration and Physical Implementation.

Lead 2 teams of ASIC designers developing ICs such as Image Sensor/Processors, Low Power SOCs, Image Sensor/Processors and Printer controllers. I was responsible for all aspects of the design flow. As a hands on role I performed Physical Design using Magma Talus and Synopsys tools.

Lead a team of 19 RTL, Analog and Physical Designers on multiple ASICs in different stages of design. The work including specification, logic design, verification, physical design, silicon validation and production engineering.

Lead the power management design team developing full on chip power management flows targeted to TSMC 65LP process and utilizing advanced low power design techniques such as multi VT, switched power islands, MVDD (1.0 /1.2V), onchip switching regulators/LDOs and utilizing DVFS.

2005-2008 Intel Corporation, Hillsboro, OR, USA

Summary: Lead of SOC Integration and Physical Design teams. Hands on role building teams, managing designs executing RTL-GDS flows based on Magma and Synopsys tools.

From March 07 – June 08 Worked in Ultra Low Power Chipset Group on new south bridge.

BE Lead for a Physical Design Team in the implementation of a Low Power south bridge chip. I was responsible for RTL-> GDS implementation and tapeout in 65LP technology using Magma PnR tools. I was responsible for synthesis, floorplaning, initial block level PnR and fullchip PnR. Worked closely with architects, RTL coders and DFT engineers to ensure fullchip could be routed with minimal congestion issues. The design was flipchip. Worked closely with packaging group on package selection and ballout to support board level work. Design was implemented across 3 sites and required extensive co-ordination.

From March 05 – March 07 Worked in Wireless Network Group on WiFi chips for Centrino based platforms.

Lead a team of 10 BE Engineers including 4 contractors over a period of 2 years. Concurrently, led a separate team of 5 engineers on Timing/SI closure for a 4 month period.

Responsible for physical design and Tapeout of 2 wireless chips (for Centrino based Platform) over a period of 2 years. This included resource management and scheduling of the RTL to GDS part of the projects as well as all flows/execution from RTL handoff to GDS tapeout. The EDA tools used were from Magma and Synopsys. I was the technical team lead for these projects and played a hands on role, being involved in floorplanning, layout, timing/SI closure and DFT insertion.

Achieved first pass silicon to production (A0) on one IC which was a high volume product and time critical for the company.

Played lead role on STA teams having to manage multi-corner (8 corner) multi-mode (23 mode) timing regression environment.

Hands on team leadership for all aspects of the Physical Design. Placed Emphasis on Floorplanning/APR for area reduction, power reduction and rapid timing closure. Used multi-Vt, mult-VDD and switchable power islands during implementation. Used Magma for floorplan and APR work and Star-RCXT /Primetime for timing closure. Used both internal and external fabs.

2002-2004 Nokia Mobile Phones, San Diego, CA, USA

Summary: Leader of Integration and Physical design team. Block level RTL developer

I worked in the CDMA ASIC Group on both front-end and back-end design activities.

Worked as physical designer for a CDMA modem ASIC. Used TI Timepilot Tools for backed flow. Used Apollo/Jupiter for floorplanning. Cell placement was performed with Physical Compiler; Apollo for routing, timing analysis was performed with Primetime. The design was more than 1 million equivalent gates in size and implemented in 130nm.

Worked with team of engineers performing TI Pyramid and Magma Backend work for 3G CDMA Baseband chip. This chip was a 90nm SoC device incorporating ARM and DSP processors, mixed signal blocks and subchips. Included all physical design work such as cell placement, clock tree design and detailed route in order to achieve timing closure of the design. I was responsible for floorplaning, layout (Magma), achieving timing closure (Primetime), meeting tight schedules,

Led the physical design effort for a 130nm Modem chip for next generation 3G BaseBand chipset using TI Pyramid and Magma design tools. I performed top level and subchip level Floorplaning and partitioning and, placed a strong emphasis on physical partitioning for design reuse. I worked on the complete backend flow for the subchip design including detailed floorplanning, power routing, physical synthesis/cell placement (Physical Compiler), detailed routing (Apollo), clock tree insertion and timing analysis. This chip design is more than 1 million equivalent gates in size, has 42 megacells. First silicon Tapeout was a working success.

Debugged Turbo decoder module for CDMA EV/DV modem. Was brought in to help the original designer find some performance related bugs. Wrote test environments to perform automatic test vector comparison (against C bit accurate model) of the internal nodes of the decoder. Found 6 bugs in the design all of which affected performance.

Architected a new version of a turbo decoder for CDMA EV/DV system. The design used half the memory of its predecessor while having improved data processing performance. Handed off the design to RTL developers for inclusion into latest generation ASIC.

Architected a micro coded framing processor for CDMA EV/DV modem. Defined the architecture and instruction set of the machine. Wrote the micro code to implement CRC generation, encoding, interleaving, symbol repetition and puncturing.

2000-2002 Conexant, San Diego, CA, USA

Summary: SOC Architect and team leader of RTL and verification team. Emphasis on design architecture, block and fullchip RTL development, verification and STA activities.

Worked in Network Access Division Group (Mindspeed) on DSL /SONET ASIC design, synthesis and verification till Mindspeed was closed in San Diego (due to 2001 industry depression).

Principal architect for a 12 channel T3/E3 to OC-12 multiplexer chip. This device breaks T3/E3 channels down to T1/E1 where they are mapped to VTs of a STS-12. Wrote Design Specification. This device was estimated to be 5 million gates and implemented in 0.13um.

Group lead of a team of 8 design engineers performing design, verification, synthesis and timing closure of multi-channel OC192 SONET/Framing processor. Wrote the technical specification and performed 90% of the high level design. Coded Channel Sequencer, Line Interface, and Microprocessor interface modules in verilog. Performed synthesis using Physical Compiler in a gates to placed gates flow. Built memories using the Virage Memory Compilers. Designed testbenches to support the different operating modes. The design was implemented in 0.15um, contains over 3 million gates and runs at 180MHz.

Architected, Designed and specified a multi-channel processor for SONET PHY processing. It was capable of processing 192 STS-1 channels or combination of STS-3c, STS-12c, STS-48c channels. It could perform ATM, POS and GFP processing. It was capable of performing virtual concatenation for up to 96 STS-1 channels. As well as architecture and design, I performed scheduling for the project and resource management. The design received the personal commendation of the Chief Technical Officer of Conexant/Mindspeed.

Architected an OC192 SONET PHY processor. Wrote Specification, performed project planning and scheduling. Architected a POS, ATM module to support 64 channels of STS-3c. Performed scheduling for the project using Microsoft Project. Design was then outsourced.

Led team of 4 Engineers in the design and implementation of a Testbench / Regression environment. Established Top Level verification environment for an 800k gate DSL/Framer ASIC . Used PLI extensively to allow the Testbench to read various configuration files for testbench control. Used PERL scripts to control the regression environment.

Developed Functional ATE vectors for DSL chip. Worked with tester engineers to debug vectors on ATE equipment.

Wrote multiple C based test/application routines for embedded ARM and 8051 micro-controllers.

Designed a test CPU system based on the ARM 9TDMI processor and used Mentor Graphics CVE (Seamless) to debug and demonstrate bootup and testcode.

Worked in “next generation DSP group” looking at Signal Processing requirements and architectures for multi-port, mixed HDSL/ADSL modem solutions. Led team of 3 engineers looking at architecture and implementation issues.

Wrote ARM sub-system design specification for next generation DSL chipsets. Specified custom cache controller for ARM9ES synthesizable core to interface to high density embedded 1T-SRAM memories. Specified “ChipView” which is a concept for controlling and monitoring the performance of multiple embedded cores via a high speed IEEE1394 port.

1997-2000 Motorola / Lucent Technologies Piscataway, NJ, USA

Summary: Architect and leader of development team. Emphasis on design architecture, block and fullchip RTL development and verification.

Originally employed by Lucent but the Division was purchased by Motorola. Worked 2.5 years as part of the ASIC design group at Consumer Products and Cellular Subscriber Sector.

Was the Technical leader for the transmitter of an IS-2000 CDMA modem (lead team of 5 design engineers and 3 verification engineers). I personally performed design architecting and partitioning for a multiple channel transmitter and captured the design using the EASE HDL block capture tool. I coded the frame assembly, convolutional and turbo encoders and, the interleaver in Verilog. I was also responsible for the control block for the TX which managed the scheduling of channels and the power down modes of the design. I designed the testbench which used the Verilog PLI interface to the Modelsim simulator.

Performed hand-coding of RTL modules and testbenches (using Verilog and VHDL).

Worked on physical layer implementation issues associated with ASIC modems. Architected a high speed version of a symbol processor for a CDMA IS95C de-modulator. This processor was micro-coded and was capable of performed pilot filtering, channel estimation, channel de-rotation, de-skewing, de-interleaving and rake finger combining for multiple channels.

As part of CDMA IS95A/B ASIC modem, designed DSP interface and Viterbi decoder modules in the demodulator. The designs were captured using the EASE HDL block capture tool and coded in VHDL. I wrote the testbenches in VHDL and used PERL scripts to run RTL and C models to compare results.

Used Modelsim for functional simulation. Synthesized using Synopsys Design Compiler ( to LSI G10 technology). Used LSI Logic Toolkit to build RAMs, generate BIST circuits and do chip floorplanning. Used Motive for static timing analysis.

1992-1997 QPSX/JTEC, Perth, Australia

Summary: Architect and leader of IC development team. Executed RTL coding, verification/regression, synthesis, DFT, floorplanning and STA

worked in System, Hardware and Software Engineering. Three years on embedded software design and four years on hardware modeling and ASIC/FPGA design. As Senior Design Engineer, performed roles from Principal designer to Project Leader. Also performed the role of Tool Manager responsible for the maintenance of existing tools, evaluating new tools and recommending the purchase of new tools.

As a Senior Hardware Design Engineer and Team Leader, I was responsible for the technical design of ASIC and FPGA chips used in ISDN (inverse multiplexing) and ATM (622Mbps SAR and Queue Manager) communication products. The design methodology used was top down HDL. For all designs I contributed the detailed functional specification, the internal architecture/design and the VHDL RTL models. I wrote testbenches and performed functional simulation for the designs using Modeltech VSIM and Vantage simulators.

The 622Mbps SAR chip was designed with an embedded custom uController which was a 96 bit micro-coded machine performing SAR, traffic policing and shaping. This processor had 6 execution units controlled from the uCode, had 3 stages of instruction pipelining, and included a single cycle priority interrupt scheduler with context switch. This device operated at 78MHz in 0.35 um technology. For this device I defined the processor architecture and instruction set specifically for the application. I then coded the RISC machine in VHDL.

Responsible for the silicon implementation of the devices including Design Capture, Synthesis (Synopsys DC), Static timing analysis (LSI internal tool), JTAG scan insertion and Flooplanning and Pin Bonding (LSI CMDE tools). Performed the technical management including design/issue tracking and formal test specification. Work also included Shell and Perl scripting for managing tests and control of the design synthesis.

Also participated in projects in the role of embedded Software engineer. I was involved in the partitioning, coding and debugging/testing of software modules using C and working with a proprietary RTOS. These modules were used in cell based communications products such as packet segmentation and reassembly modules, routers and gateways. The designs included software implementation of communication protocol stacks, address filtering and management tasks such as startup, download and usage charging/billing.

Performed Design and coding of embedded software for "smart card" Stored Value Card System. Worked within the Operating system group to write drivers for the hardware and also write self test code. The software was written in C/C++ and built around the Nucleus Plus real time executive from Accelerated Technologies.

Education and Training

Degree: Bachelor of Engineering (B.E.) from West Australian Institute of Technology (now called Curtin University of Technology). Major in Electronic and Communications Engineering.

Professional training in Magma Blast and Talus, ICC, Cadence VoltageStorm and Conformal, Apache Redhawk, Mentor Calibre, Synopsys Design Compiler topographical, PT/PTSI.

KEYWORDS: ASIC, SOC, FPGA, RTL, HDL, VHDL, ARM, ARC, AHB, Verilog, Design Compiler, VCS, Synopsys,

Primetime, PTSI, Physical Compiler, ICC, Magma, Blast, Talus, Perl, TCL, Scan, BIST, hardware, software, BSEE, Linux, Manager, Lead, Microsoft Project, Python, SERDES, ARM, AXI, DDR3, FPU, Aurora, JESD204B, Ethernet, floorplan, Layout, Place and Route, FCBGA.

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