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Engineer Design

Richardson, Texas, United States
March 12, 2019

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Mobile: +1-469-***-**** Richardson, Texas-75080

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An RF/Antenna and microwave engineering enthusiast, experienced in various RF test setup measurements and Antenna design and measurements, well versed with various simulators involving RF and Antenna Design. Seeking to leverage my skills for the RAN/RF Engineer role at KCCTech.


The University of Texas at Dallas. (Aug 2016- Dec 2018)

Masters of Science in Electrical Engineering, (Specialization in RF and Microwave Engineering) GPA: 3.42/4.00

Relevant Coursework: RF and Microwave Circuits, RF and Microwave Amplifier design, RF and Microwave Systems, Microwave Design and Measurements, RF Power Amplifier, Active Microwave Circuit Design, Fields and waves, Analog Integrated Circuits, Antenna Engineering and wave propagation.

KIIT University. (July 2012- May 2016)

Bachelors of Technology in Electronics and Telecommunication Engineering. GPA: 8.29/10


Engineering Tools: AWR (MWO, VSS, Axiem), Ansys HFSS, FEKO, Antenna Toolkit (MATLAB), Cadence Virtuoso.

Lab Instruments: Vector Network Analyzer, SOLT calibration, TRL calibration, RF Power Meter, Signal Generator, Crystal Oscilloscope, Spectrum Analyzer, Noise Figure meter, Anechoic Chamber.

Programming Languages: Python (Basics)

Wireless Communication: Basics of Wi-Fi, Bluetooth, LTE,5G,4G.


MobileComm Professionals Inc. (Jan 2018-Apr 2018)

Testing and obtaining data for various RF signal measurements, GPRS, LTE, EDGE.

Analyzing signal strength of various signals on TEMS

Analyzing the collected data and generating RF engineering reports.


Design of a Multi-stage power amplifier MMIC. (Oct 2017-Dec 2017)

A two-stage power amplifier MMIC was designed at 9GHz using concepts of power splitting and power combining.

Design specifications like gain of 26dB, PAE of 32 % and other specifications were achieved and the MMIC layout was designed.

Design of a single stage low noise amplifier. (Nov 2017-Dec 2017)

A single stage LNA was designed at 1.5GHz by choosing specific bias conditions, gain of 18dB and noise figure (NF) of 0.66dB.

Gain Analysis, Noise figure (NF) analysis, input matching, output matching, stability analysis and bias network analysis was performed.

Design of Class A and Class B Power amplifier. (Sept 2017-Oct 2017)

FET DC-IV analysis was used to define bias regions for a Class A and Class B Power Amplifier.

Load line analysis, output power calculations, Non-Linear simulation (HB) analysis was used to calculate gain, PAE, IP3, P1dB.

Design of a 2 GHz single stage amplifier. (Sept 2017-Oct 2017)

Design of the bias network using various SMD components, RF choke using transmission lines, bias conditions of Vce=2V, Ice=20mA.

Design of single stage amplifier on FR4 substrate, by using lumped input and output matching networks, and achieving gain of 13dB.

Design of a 2-stage differential amplifier. (Nov 2018-Dec 2018)

A two-stage differential amplifier was designed and device size of each transistor was calculated and optimized for all the specifications.

Gain, Output voltage swing range, Common mode rejection ratio, input common mode ratio, phase margin were measured.

Design of a patch antenna for bandwidth optimization. (Sept 2018- Dec 2018)

A patch antenna on FR4 substrate was designed with a slot, the slot dimensions were optimized so as to achieve maximum bandwidth.

Parameters like efficiency, S11, VSWR were measured and also compared with the VNA results, and polarization patterns were observed.

Design of a dipole antenna. (Aug 2018- Sept 2018)

A half wave dipole antenna of length 0.475λ and radius 0.3mm was designed in HFSS and FEKO at a center frequency of 1GHz.

Performance parameters like gain of 2.39dB, VSWR of 1.07, bandwidth of 0.08GHz were calculated.

Microwave Design and Measurements Lab. (Jan 2017-May 2017)

Design, measurement, troubleshooting of passive components like Microstrip resonators, Wilkinson Power divider, directional coupler, design of low pass filters (Chebyshev and Butterworth) at 2.5GHz on FR4 substrate.

PCB was connected to the VNA and S-parameters were observed and compared with the measured results.

Design of 1.3 GHz voltage-controlled oscillator. (Oct 2017)

Design of the Varactor, the varactor model was reverse biased to extract the capacitance of the diode for the reverse voltage.

The entire VCO was designed at 1.3GHz with a tuning range of 200MHz and output power of 11dBm.

Design of 2.1 GHz balanced mixers. (Oct 2017-Nov 2017)

A rat race coupler was designed to define the delta port and the sum port and various S-parameters were observed.

Design of the complete mixer using diode matching circuit, IF filter. Conversion gain of -12dB, isolation between ports was measured.

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