ANTHONY F. GALLIPPI
email@example.com ● 510-***-****
AREAS OF EXPERTISE
Engineering Leader – Engineering Design & Development – Technology R&D – Manufacturing Operations – Machine Learning – High Performance Computing – Embedded Systems – Networking – Consumer Electronics – High Speed Ethernet – Signal Processing / DSP – Board Design – PCB Design – FPGA Design – Digital / Analog – Mechanical and Thermal Design – Software Design – CM / ODM Management – NPI – Product Lifecycle Process PROFESSIONAL EXPERIENCE
NVXL TECHNOLOGY – Fremont, CA April 2017 to January 2019 Provider of high performance computing (HPC) systems for compute acceleration and machine learning Senior Director, System Architecture and Hardware Development
● Delivered compute acceleration product that achieved aggressive performance, power and thermal targets by providing hands-on technical leadership and mentoring to development team, by partnering with ODMs, and by ensuring utilization of latest CPU, high-speed bus (PCIe 3.0), SDRAM memory (DDR4), FPGA technology, and NVMe protocol.
● Co-architected scaleable platform that achieved acceleration via FPGA, GPU, ASIC modules that utilize high speed memory and SSDs within a framework that accommodates peer-to-peer communication and the capability to provision hardware from a resource pool in order to achieve desired workload and performance targets across diverse applications.
● Demonstrated performance advantages for various computationally intensive workloads including deep learning (DLA), genomics (PairHMM), transcoding (HEVC/H.265), encryption, compression.
● Enabled seamless mode switchover of platform to desired functionality for any supported application, via static and dynamic reconfiguration of FPGAs facilitated by software.
● Eliminated the need for platform silos for each acceleration technology by developing the capability to dynamically provision pooled hardware resources and perform mode switchover, thereby providing customer an opportunity to reduce data center footprint and total cost of ownership (TCO).
● Utilized design reviews to ensure first pass success of board designs and mechanical designs, and to ensure optimized designs that permitted better performance while pushing power and thermal limits.
● Delivered $160,000 in cost reductions to hardware development expenses by leveraging overseas contractors and CMs where feasible, without compromising schedule or quality.
● Hired and efficiently managed headcount, contractors, ODM partners, CMs and capital equipment against aggressive development schedule to deliver product with $800K annual budget. SOLE PROPRIETOR – San Francisco Bay Area August 2014 to March 2017 Provider of engineering and technology expertise to consumer electronics companies Engineering and Technology Consultant
● Provided expertise in engineering design, development processes, new technology, design verification testing
(DVT), design for test (DFT), design for manufacturability (DFM), regulatory compliance (EMC, EMI, safety) to clients developing consumer electronics products including electronic credit cards and smart door locks.
● Advanced hardware technology for an electronic credit card product that resulted in a better than 95% transaction success rate across 50+ swipe (magstripe) and chip (EMV) style card reader models tested in house as well as 1000+ randomly tested card readers in the field.
● Improved electrical and mechanical design of electronic credit card utilizing flexible PCB, battery and LCD to permit passing the most stringent Mastercard compliance tests that included bending stiffness, resistance to heat and humidity, peel strength, overall card warpage.
● Introduced quality management, cost modeling (i.e., COGS), manufacturing partnerships (ODM, OEM, CM).
● Originated process introduction and improvement including product lifecycle process, new product introduction (NPI) process, to improve execution efficiency and TTM performance, and reduce risk. GIGAMON – Santa Clara, CA April 2009 to May 2014
Provider of network equipment for intelligent network traffic visibility. Director of Hardware Engineering
● Reduced development schedules 15% by originating design reuse strategies and development methodologies across electrical, mechanical and software developments that included peer design reviews to improve quality of designs and ensure first prototype success—and by identifying, mitigating cross-functional dependencies.
● Co-architected H-series platform and designed Ethernet switch fabric, control & power modules, backplane.
● Transformed traffic visibility market by delivering first terabit per second capable system; milestone achieved by overcoming challenges of latest technology adoption (e.g., deep packet inspection (DPI), Ethernet, PCIe).
● Grew a successful team that delivered more than 25 products across 10 platforms to market, to fill product portfolio, as company completed successful IPO.
● Succeeded in consistently meeting time to market (TTM) goals by working collaboratively with peer new product introduction (NPI) organizations to establish and follow lean NPI process and product lifecycle process.
● Ensured efficient hardware and software designs by utilizing design reviews, resulting in products meeting green power standards and exhibiting the best performance per watt of power consumed in the industry.
● Improved product launch quality by enforcing adherence to DFT, DFM, DFx and by increasing scope of DVT.
● Efficiently managed headcount, contractors, CMs, ODMs, OEMs, vendors and capital equipment against aggressive product development and sustaining commitments with $4 million annual budget.
● Maintained 100% employee retention by emphasizing coaching, empowerment and team building. CITRIX SYSTEMS – Santa Clara, CA October 2007 to December 2008 Provider of application networking products for server virtualization, web application delivery, SSL/VPN, branch office application delivery, and WAN optimization. Director of Hardware and Manufacturing Engineering
● Launched 5 new hardware platforms in 8 months, by mentoring and providing technical leadership to team, and by improving NPI process, vendor and component qualifications process, DVT and manufacturing test.
● Consistently achieved TTM goals by efficiently managing headcount, contractors, ODMs, OEMs, CMs, vendors and capital equipment against aggressive product development, regulatory compliance commitments.
● Trained global DF centers with capabilities of order fulfillment, SW download, SW upgrade, SW downgrade, licensing, RMA replacement and RMA repair, thereby reducing the fulfillment burden on US fulfillment center by 24% and increasing fulfillment efficiency across geos while decreasing operations expenses.
● Implemented an electronic software delivery model to demand fulfillment (DF) centers in order to avoid shipping of media, thereby eliminating delays associated with shipping and customs, and enabling DF centers to respond immediately to new software releases or time-sensitive software changes.
● Improved product field quality to 99.5+% for first 30 days and 98+% for first year by establishing and main- taining a comprehensive set of quality metrics for each product including return rates, DOAs, failure category distributions, and then repeatedly interrogating metrics to identify and fix the highest defect contributors.
● Led an internal tiger team to solve a critical bug escalation for a new SW release within 3 business days, resulting in increased satisfaction from a major customer.
● Implemented a field replaceable unit (FRU) model for products in the field that permitted shipping FRUs
(e.g., power supplies) directly to customers instead of customers return shipping (RMA) entire systems, thereby reducing RMA burden by 22%, reducing operations expenses, and improving customer experience. EDUCATION
Ph.D. in Electrical Engineering – University of Southern California – Los Angeles, CA Dissertation: A Machine Learning Approach to Multilingual Proper Name Recognition M.S. in Electrical Engineering – University of Southern California – Los Angeles, CA B.S. in Electrical Engineering – Carnegie Mellon University – Pittsburgh, PA HONORS AND ASSOCIATIONS
Eta Kappa Nu, Tau Beta Pi, TRW S&EG Fellowship, USC Merit Fellowship, Charles Gulentz Memorial Scholarship