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Analog RF LAYOUT DESIGN Engineer

Woodlands, 737788, Singapore
March 08, 2019

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Mobile • (+65) 91920114


Dynamic 12+ years Industrial experience in Analog/RF Layout Design.

14nm(FinFET), 22nm(FDSOI), 28nm, 40nm etc working exposure.

Expert in Analog layout techniques and guidelines [Matching, Antenna, latch-up etc].

Understand critical/sensitive RF layout technique [Isolation, Shielding etc].

Proficiency in interpretation & debugging DRC/ERC/LVS reports & PEX extraction.

Scripting expertise in Cadence SKILL (P-Cell & design automation), TCL, C-shell, etc

Expertise in Cadence & Mentor, Virtuoso(ICADV12, 6.1.x, 5.1.x), PVS & Calibre.

Full Chip DRC, LVS verification sign off for Customer IP’s & suggestion for correction. WORK EXPERIENCE

Global Foundries Pte Ltd. (Singapore)

Principal Engineer Oct2010-present

• Analog/RF block-level custom layouts/ IP development & verification sign -off.

• Development of full chip/Modelling test-chip for active & passive devices.

• Review MEBES data and verifying Mask generations & sign-off before mask release.

• Scripting for tool/Design automation & test-chip development flow. (SKILL, TCL etc).

• Responsible for verification checks DRC, LVS, DFM, Density, Antenna, LatchUp etc.

• Identifying areas of complexity that needs early investigation. ST Microelectronics

Design Engineer Aug 2009 -Sept 2010

Assigned for Analog layout design & verification for wireless IP development. Layout design of complex Analog/ Mixed signal blocks using Virtuoso layout Editor (Cadence). Verification (DRC, LVS, RCX) of the design blocks using Calibre. Key blocks for different Projects undertaken:

• BGR, OP-Amp, VCO etc.

RFIC Solutions Inc.

Senior Layout Engineer Oct 2007– July 2009

Assigned for RF/Analog layout design & verification. Layout design of complex RF & Analog blocks using Cadence Virtuoso & Advanced Design System (ADS). Verification (DRC, LVS) of the design blocks using Assura & Calibre.

Key blocks for different Projects undertaken:

• PLL, LNA, Power Amplifier, Mixers, Oscillator, Band Pass Filters etc Joints chip Technology (P) Ltd. India

Senior Layout Engineer May2006 – Oct2007

Engaged in development of Standard Cell Libraries & Custom Cells, physical verification using Cadence virtuoso & Mentor’s Calibre for DRC/LVS.

• Standard Cell Library development,(~650 cells) for 0.18u technology. SUBHASH SHARMA Page 1 of 2

Connect Logic. India

Layout Trainer Oct2005 - May2006

• PDK installations and creating environment, Automation of design flow for smooth flow,

• Tools troubleshooting and support design staff to solve layout, DRC, LVS problems.

• CAD tool setup, management and installations of PDK’s. Experience with TSMC, IBM & Triquint foundry on Cadence & ADS.


IC Layout : Cadence (Virtuoso ICADV12, 6.1.x, 5.1.x), ADS Physical Verification : Assura & Calibre ( DRC, LVS and RCX) Design Entry : Virtuoso Schematic Composer, Tanner S-Edit Operating System : Linux, Unix, Solaris, Windows

Programming /Script

SKILL (Cadence) : Scripting Tool automation & P-Cell development (Advance). C-Shell, TCL : Scripting (Intermediate)


• SPOT LIGHT Award (2018) for outstanding /significant work within limited resources. EDUCATION

IndraPrastha (IP) University, Delhi

• Bachelor of Technology, June/2004

Electronics & Communication

ISRDO, Vivek Vihar, Delhi. July/2005

• Linux RHEL-3 System Administration

Place: Singapore (Subhash Sharma)


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