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Engineer Engineering

Location:
Redwood City, California, United States
Posted:
March 07, 2019

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Resume:

HASMUKH PATEL

**** **** ******

Santa Clara, CA *5051

408-***-****

E-mail: ac8pm7@r.postjobfree.com

OBJECTIVE

A position as Manufacturing/ Engineering Technician.

Experience and Technical skill in the following area.

Test, repair defective devices, image analyses for digital x-ray flat panel detector. Extensive use of laser for repairing defective devices.

Metal deposition, CVD and dry/wet etching, EPI, Implant, diffusion.

Metrology tools calibrations and wafer measurements, recording data into corresponding SPC files or database, basic tool maintenance.

Automated and Manual Wafer level testing for inline data and device characterization.

Strong skills in problem solving, running experiments, collecting data and analyzing data.

Microsoft Word, Excel, PowerPoint, Lotus Notes, Documentum, JMP Statistical Analysis, RS1, Data Power, and LTL.

Varex Imaging/Perkin Elmer – Optoelectronic, Santa Clara, CA Mar. 2002 - Present

Test and Repair Technician - III

Responsible for intermediate defect tests for URP, P-rad, T-rad, Cardiac, Angio and Combo products used as X-Ray detectors. Performed initial image, short, open tests and Roger Novel on FET, ITO using RAD D Tester. Repaired defective devices using automatic file and manual using laser.

Performed Functional test for FET, Indium Tin Oxide (ITO) and Light imager process steps for RAD-41cm panels using RAD F Tester. Analyzed images and repaired noise on all products after Functional test.

Achieved daily throughput goals every day consistently. Tracked production lots using PROMIS MES system. Taken pictures of non repairable defects-area, split and hold panels

for engineering disposition.

Scion Photonics, Milpitas, CA Nov. 2001 – Feb. 2002

Associate Engineer

Processed wafers in etch area using 5200 AMAT Centura System for oxide and silicon etch process. Ashed wafers in Mattson asher and performed sulfuric clean using Verteq Wet Deck. Performed FICD measurement using Micromatric metrology tool.

Supported maintenance personal in Preventive Maintenance (PM) and qualified tool after PM.

Performed weekly etch rates for PSG, BPSG, Thermal Oxide and particle monitors, collected data and created charts on Excel.

LSI LOGIC, Santa Clara, CA May, 1999 – Sep, 2001

Assistant Engineer

Generated R&D run cards for a 0.13um process development. Splited lots and implemented experiments at various process steps.

Optimized 100% of 0.13um front-end process integration on shallow trench isolation, gate oxide schemes, and transistor implant matrix.

Performed device characterization (transistors, resistors and capacitors) using HP4156B Semiconductor Parameter Analyzer (eg. I/V curve, Vt, resistance) and 4284A Precision LCR meter for CV measurement with 0% errors.

Managed Electrical Test requests so data was received on time and new process could be delivered on schedule

NATIONAL SEMICONDUCTOR, Santa Clara, CA May, 1985 - Apr, 1999

Senior Process Technician

EPI, Diffusion, Implant and Thin film Area

Responsible for process engineering tasks on NV-GSD/200E (High Current Implanter), NV-8200P (Medium Current Implanter), NV-GSD/VHE (High Energy Implanter), and Applied Material Centura RTP and AG Associates 8108 RTP.

Supported the development for the state-of-the-art 0.25 micron and 0.18 micron implant

process and met schedules consistently.

Solved major Vtp variation problems that ultimately improved production yield.

Developed and characterized 0.25um Titanium and 0.18um Cobalt process and delivered on time.

Performed tool qualification and engineering experiments of Semitool furnaces for Oxidation, Poly deposition, and CVD Nitride deposition.

Wrote process specification documents for Source/Drain anneal, Titanium salicide, Cobalt salicide and Implantation processes.

Conducted training to manufacturing associates on operation of Implant, RTP and supporting equipment.

Trained in the operation of Semitool furnace, CFM wet etch, Verteq Reclaim Wet Deck, SMS Wet Deck, ADE wafer warp measurement, Prometrix, Tencor 6220, Tencor AIT, JOEL SEM, AFM, Nikon Wafer Inspection, SDI station 3030, Rudolph Ellipsometer and Thermawave tools.

Maintained Cp, and Cpk for production processes.\

Supported 6” process equipment, Applied Material 5000 series for tungsten CVD, TEOS deposition, and oxide and nitride passivation process.

Sustained EPI process on Gemini EPI reactors, 7600/7800 Applied Material and Unpack XX reactors for discrete and linear technology. Conducted and evaluated DOE. Familiar with SRP.

Sustained thin film processes such as tungsten CVD, TEOS deposition, nitride passivation, RTP, Spin On Glass, and multi-layer PSG/BPSG oxide deposition using Novellus Concept – I/PECVD.

EDUCATION

AS in Electronics from Mission College, Santa Clara, CA.

BS in Electrical Engineering from SP University, India.

CMOS Process and Device Technology, Process Device and Integration, DOE, and SPC classes.



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