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To be involved in work where I can utilize skill and creatively involved with system that effectively contributes to achieve personal as well as organizational goals. Academic Profile:
Advanced diploma in ASIC Design (6 months) –RTL Verification. RV-VLSI Design centre.
M.TECH (VLSI and Embedded Systems) from G.Pulla Reddy institute of technology, Kurnool and affiliated to Jawaharlal Nehru Technological University, Anantapur with an aggregate 71%
B.Tech ECE from Dr.K.V.Subba Reddy College of Technology, Kurnool and affiliated to Jawaharlal Nehru Technological University, Anantapur with an aggregate 69%.
Intermediate from Narayana Junior College affiliated to Board of Intermediate Education, A.P in the Year March/Apr 2011, with an aggregate 74.6%.
Secondary School Certificate from Montessori English Medium High School affiliated to the Board of Secondary Education, A.P in the Year March/Apr 2009, with an aggregate 80.5%.
Knowledge of UVM.
Knowledge of functional coverage and code coverage. Knowledge in logic design.
Writing test cases.
Writing verification plan.
Domain specific project:
FIFO verification in system Verilog
To verify the design under test of a FIFO using all the components of a test bench as generator, driver, monitor, scoreboard.
SATA Link Layer Verification in UVM
To verify the SATA link layer at different situations by writing the test cases for the signals to be manipulated.
Academic Project (B.E):
Project title: Android and Bluetooth based unmanned firefighting robotic vehicle using microcontroller.
The need for this firefighting robotic vehicle is to control the fire accidents in any nuclear power plants, chemical facilities. To develop the prototype of the autonomous unmanned firefighting vehicle that would be able to fight efficiently against fires in hazardous environments, particularly where men and firemen are highly jeopardized. FIREROB is able to enter into the heart of fire, operate and navigate reliable and recognize different objects and remove flammable or dangerous material.
Academic Project (M.E) :
Project title: Design of a fully integrated receiver analog baseband chain for 2.4GHz ZigBee applications.
The analog base band chain consists of the three main building blocks such as BPF,VGA and ADC. In this base band chain I have designed an VGA block in which it will accomadate the high variations in the signal and sends the stable signal to the next block. Resources
Extra circular activities :
Won prize in the throw ball competition.
Participated and won prize in paper presentation.