Graduate Research Assistant

Lakshmiteja Vipparla

** ***** **, *** * • Edwardsville IL 62025 • 618-***-**** • ***********.********@*****.*** Objective:

I desire to work in a challenging Electrical Engineering environment demanding all my skills and efforts where I can apply the knowledge, talents and ideas showing my integrity, honesty, commitment and excellence; participating enthusiastically in activities that promote my continuous success and learning. Education:

Master of Science in Electrical Engineering (Integrated Circuit Design) Expected: May 2019 Southern Illinois University Edwardsville (SIUE) Edwardsville IL Graduate specialization: Advanced Digital System Engineering, Digital VLSI design, GPA: 3.6 Analog CMOS Integrated Circuit Design, Mixed-signal VLSI design, Analog Filter Design Bachelor of Technology in Electrical and Communication Engineering May 2016 JNTU Kakinada Andhra Pradesh, India

Technical Skills:

CMOS process for IC Design like:

TSMC 0.50 μm, ON 0.50 μm, AMS 0.35

μm

Analog and mixed signal simulators:

Spice, Spectre, UltraSim, amsSpectre,

Monte carlo Analysis

IC layout verification tools: Calibre/

xCalibre from Mentor graphics, assura

(DRC, LVS, PEX)

Knowledge of discrete electronic design:

BJT, MOSFETS, Power devices,

Implementing Analog Circuit Theory

Connectivity driven layout tools:

CCAR (Cadence Chip Assembly

Router),

Space Based Router

Design tools: Xilinx ISE, modelSim,

LTspice, MATLAB, Cadence Design

Software (Composer, Virtuoso Version

IC 5.1.41 and IC 6.1, RTL Compiler,

Silicon Encounter)

Languages:

Verilog-A: Industry standard modelling

language for analog circuits

Verilog/System Verilog: Hardware

Description language to model

electronic systems, used in the design

and verification of digital circuits

Python: Used in Analog and mixed

signal extensions

C programming/Embedded C/JAVA

Operating systems: Linux, Windows –

All versions, IOS, CentOS

Professional Experience:

Graduate Research Assistant August 2018-Present

IC Design Research Laboratory, SIUE Edwardsville, IL Advisor: Dr. George L Engel

Develop and design complex, multi-channel, low power integrated circuits

Responsible for all aspects of Analog/Mixed signal ASIC design involving design, simulation, checking (DRC and LVS), layout, and testing

Identify and address few performance issues of CFD chip (Pseudo Constant Fraction Discriminator), which is a custom ASIC used in nuclear physics experiments

Assist in layout of some parts (Leading Edge discriminator and Zero-Cross discriminator) of CFD

Successfully submitted CFD chip for fabrication in December 2018 through MOSIS

Currently working on HINP64C chip (Heavy-Ion Nuclear Physics-64 channels)

Utilized Cadence Spectre, Virtuoso Layout Editor, Virtuoso AMS designer and SoC Encounter tools, Solid understanding of transistor-level analog circuit design

Communicate results effectively by preparing reports and presentations Vipparla, 2

Graduate Teaching Assistant August 2018-Present

Electrical and Computer Engineering Department, SIUE Edwardsville, IL Conduct lab sessions for Electronic Circuits-1 and Circuit Analysis-2 includes courses

Assist students in the designing of OP-AMP based circuits in LTspice, while also helping students run simulations

Guide students during the building of the circuits on Breadboard; follow-up and check students work upon completion

Educate students about circuit operations, functions and output waveforms on Digital Oscilloscope display on simulation

Respond to student questions regarding coursework

Evaluate and grade lab reports and quizzes in a timely manner Assistant Systems Engineer Jun 2016 - July 2017

Worked in Production (Level 3) Support for one of leading Credit Card (AMEX) & Travel Services Company, based out of USA - TATA CONSULTANCY SERVICES PVT. LMTD, INDIA

Actively monitored and managed the availability of the web application and installed systems.

Responsible to liaise with other IT Professionals, third parties in problem resolution.

The availability of the web applications is monitored and maintained using Gomez, Splunk, and Service Now tools.

Projects:

Master’s Project January 2019-Present

SIUE Department of Electrical Engineering Edwardsville, IL

Design, simulate, and layout of Pad Frame, Bonding diagram, and Common Channel in HINP64C chip, which is used in the Detection and Monitoring of Radiation. Verilog Projects

Adding instruction/data memories to implement instruction fetch, LW, SW 2018

Implement and simulation of pipelined register bank / ALU design 2018

Design of MIPS 32-bit ALU 2018

Verilog-A projects

Design of Rauch Filter using Verilog-A/ Cadence Spectre Simulator 2018

Two stage 6-Bit DAC using Verilog-A/ cadence spectre simulator 2018 Design, simulate, and layout in cadence virtuoso software using calibre, assura (DRC, LVS, and PEX) tools

Folded cascode OTA (Operational Transition Amplifier), Nowlin Circuit 2018

Temperature independent current reference circuit 2018

16-Bit carry adder, and 4-Bit magnitude comparator 2017 Design, simulate the circuit in LTspice and built it on the Breadboard

6

th

order Chebyshev Tow-Thomas bandpass filter for use in processing ECoG signals from a BCI

(Brain Computer Interface) 2018

Heartrate Monitor Circuit 2018

Design of Infrared Transmitter and Receiver 2018 Matlab Project

Implemented noise removal techniques in image processing 2018 Undergraduate Projects 2016

JNTU Kakinada Andhra Pradesh, India

Developed an underground cable fault distance locator on PCB using Microprocessors and Micro controllers, and coded up the functionality using Embedded C programming

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