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Project Design

Suwon-si, Gyeonggi-do, South Korea
March 03, 2019

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Hishe, Hintsa Fisseha

South Korea, Suwon

Contact number: +821*********

Email ID:


Education Detail:

à BSc in Electronic Engineering at Ajou University, South Korea with 3.83/4.5 GPA. à Certificate in MOSFET fabrication process from Ajou University, South Korea. à Certificate in Embedded C programming from Ajou University, South Korea. à Certificate in Korean Language from Kyunghee University, South Korea. Work Experience:

à Sep. 2017 – present: Intern at Electron device lab (EDL), Ajou University, South Korea.

à Jun. 2016 – Aug. 2017: Intern at Antenna design lab, Ajou University, South Korea. Technical Skills:



Design and Simulation



Languages / HDL

• Multimeter

• Oscilloscope

• STA (Semiconductor Test

and Analyzer)

• PSPICE and ADS (Circuit

simulation software)

• HFSS (Antenna and RF

simulation software)

• Verilog HDL, VHDL, C,

MATLAB, Assembly



• Recessed Channel Synaptic Transistor (RCST) for Neuromorphic Applications, H. H. Fisseha, H. Kim, S. Kim.

Major Awards:

• 2014 – 2019: Recipient of Korean Government Scholarship Program (KGSP). Language Skills:

• Native level


• Full Working Proficiency


Sample Projects:

à Design of a 10 floors Elevator (Finite state machine) using Verilog HDL– Final project for my Digital Systems Design class.

à Subthreshold Swing analysis of MOSFETs using SiO2 and High K materials– Final Project à Pomodoro watch count down (Finite state machine) using VHDL – Final project for Logic Circuits class.

à Logic Control Unit to control the Connection between CPU, RAM and NAND Flash – Final Project for Computer Architecture class.

à Band Pass Filter using Op Amp and RC circuit – Final project for Electronics Experiment Class.

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