Susan Peinkofer - Senior Layout Design Engineer

**** ** ***** ***. #**, Portland, OR 97229 503-***-**** ac8jjl@r.postjobfree.com

Summary:

Lead Layout Designer and Senior layout engineer roles - Delivered clean Die and Layouts with attention to: Floor planning, integration and schedule tracking. DFM including well proximity and LOD, density and isolation rules. Signal Coupling, substrate and power/GND NOISE reduction. Device matching. Reliability issues such as EM/IR, Latch up, Antenna rules, good ground/power strategies. Experience with tape out procedures and bond diagrams. Interface with offsite circuit and layout designers.

DRC ERC LVS Density using CALIBRE, Dracula, ASSURA verification tools and Cadence 6.17 XL, schematic entry for dummies and understanding of inherited connections. Used recommended rule checks. CMOS BICMOS SOI Processes in 130nm to 28nm and everywhere in between.

RF, Analog, and Mixed Signal including multiple voltages and grounds, Differential pairs, transmission lines, Low Power, High Speed, High Frequency chips which required good communication with team members.

Analog Devices: 6/2013- 1/4/2019 Wilmington, MA and Beaverton, Oregon.

45nm process on both TSMC and IBM SOI process, microwave product lines. Amplifiers, multiplier and attenuator 35nm and 50nm processes, Lead layout Designer on ASIC mixed signal sensor chips. Opamps, filters, capdac, timing, bias currents, digital pin placements, top level integration of new designs and revisions to name a few.

Luxtera Inc.: 4/2012 to 8/2013 - Carlsbad, CA

High speed, high frequency layouts. Block Level planning of RX, TIA power amplifier. 28nm

Parasitic minimization of layouts with the use of RC extraction tools.

Vitesse Semiconductor: 8/2009-11/2011 Lake Oswego, OR – office closed

Lead Layout designer for high frequency video chips. 130nm and 65nm. SERDES top level database management including integration to final tape out. Block level planning and layout for RX and VCO, PLL, Equalization and peripheral logic, SWITCH CORE.

Contract Roles: 1996-2009

Cadence Design Systems: Columbia Maryland - Low power, low noise hearing aid device. 40nm

Analog Devices - Sandy, UT 45nm digital clk drivers to Datapath core.

Qualcomm - San Diego, Analog TX, eco’s, CLK IO pad driver, Module top level assembly and block level analog layout including TX. Deep nwell processes in 65nm to 32nm.

Philips Medical Devices - Bothel, WA Ultrasound circuits using AMISi3t80 process. Digital interface to Analog core. Converted layouts for XL compatibility and helped debug top level

Toshiba - Bloomington, MN - ESD, BIAS, Pad ring, analog layouts in 65nm

Sun Micro Systems - Sunnyvale, CA Datapath adders, cache, PLL

RAMBUS - Chapel Hill NC & Bay area ESD, ECO’s, Bump process conversion, Analog Layout.

Intel Corporation: 2/1988 - 2/1996 Hillsboro, OR

486/586/686 chip sets. Lead on instruction and control BLOCKS including PLA, ROM & custom.

Cache and Datapath experience. In house tools. Helped design and test top level floor planning tool. Created and tracked layout schedules. Special attention to EM/IR. Clock and power

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