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Engineer Design

Location:
Wadsworth, Ohio, United States
Posted:
January 30, 2019

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Resume:

Shashank

Upadhyaya

Electrical Engineer

Personal Info

Address

**** * ******** **** **

Apt # S7, Medina, Ohio

44256

Phone

361-***-****

E-mail

ac8cbb@r.postjobfree.com

LinkedIn

www.linkedin.com/in/shashank-

upadhyaya

Skills

RTL

Advanced

Python

Advanced

Verilog HDL

Advanced

VHDL

Advanced

MATLAB

Expert

LT Spice

Expert

Multisim

Intermediate

Xilinx

Intermediate

Cadence Virtuoso

Intermediate

Meticulous and self-motivated person with 3 years of professional Electrical Design experience. Dependable and experienced Electronics Engineer with an excellent customer satisfaction and project completion record. Efficient in conveying complex technological theories and concepts to a wide variety of audience in a clear and comprehensible manner. Committed to creating an atmosphere of exceptional employee morale. Proficient in circuit theory, sustainable electric energy, trade practices and techniques, and digital electronics and design. A dedicated team player with an extensive knowledge of electrical engineering concepts and a creative aptitude for product design and development.

Experience

Aug 2014 -

Aug 2016

Design Engineer

SOULPRO INFOLOGIX PRIVATE LTD

Planned, designed and developed tools, engines and electrical equipment resulting in 18% increase in efficiency

Worked with architects and designers to develop technique specifications and analyze results in order to improve product quality and meet design intent

Performed RTL code coverage, assertion coverage, and gate level simulations. Worked closely with architecture and RTL designers and developed comprehensive verification plan based on IP core standard specification

Apprehended high speed CPU data fabric architecture and developed verification plans and tests to verify complex features of chip. Developed productivity through process/tool/methodology solutions and took step towards reusable and maintainable code that can be used over multiple generations of CPU/GPU products

Developed advanced verification environment and test bench components in System Verilog using VMM or UVM Methodology. Adopted new verifications methodologies that led to efficiency improvements. Developed verification and environment test bench components such as BFMs and checkers

Worked on Infrastructure including developing scripts and tools for efficiency quality improvements and executed power aware verification

Developed Verification IP that can be reused at different levels of verification: block level, sub-system level, SoC level etc

Planned Workforce use, space requirements and equipment layouts to optimize workflow which led to a 10% increased workflow in year one

Jan 2014 -

Jul 2014

Electrical and Electronics Engineering (Internship) SOULPRO INFOLOGIX PRIVATE LTD

Performed latch up functional simulations on various pads and tested the results with practical latch up stress on silicon parts

Performed water level micro-probing on I/O pad circuit for latch up characterization (silicon testing)

• Debugged layouts and improved floor planning to enhance latch up tolerance Upgraded Simulations, Layouts and designs utilizing Cadence Virtuoso, Caliber and MICA tools in LINUX environment

Worked with hardware engineers, PCB designers and fabricators for development and sustaining of actual products. Specified PCB contour and performed components placement in cooperation with mechanical and hardware developers

• Worked on electronic schematics and created a 3D model for PCB footprints

• Worked with engineering documentation systems and structures Proficient in electronic circuit and measurement techniques, and Schematic drawings

HAAR Cascade

Intemediate

Eclipse

intermediate

8051,OPEN CV, PIC

intermediate

System Verilog

Advanced

Verilog

Advanced

PCI

Intermediate

Communication and Writing Skills

Expert

Education

Sep 2016 -

May 2018

Masters in Electrical and Electronics Engineering, Texas A&M University

Graduated with 3.2 GPA

Jul 2012 -

Jul 2016

Bachelor of Engineering in Electronics and Communication Engineering,

Jawaharlal Nehru Technological University

Graduated with 3.1 GPA

Additional Activities

ACADEMIC PROJECTS:

Gesture Control and Face Recognition Using Image Processing: (Open CV, HAAR Cascade)

Design of an Operational Amplifier: (T-Spice)

Real Time Clock - RTL Design:

Design, Simulation and Layout of a Synchronous 4-bit FIFO with Empty/Full indicators: (Cadence Virtuoso):

Design and Implementation of Data Acquisition module for Radar System: We have chosen the method called gesture control technology which means a gesture (both Facial and Hand made gestures) based human-computer or human-machine interface system, where the user can control the device using purely gestures as input and on the side the computer can recognize the user based on his/her facial features This technology helps to build bridge between physical world and digital world.

Implementation of low power and high performance Full Adder using Transistor LECTOR Technique.

Effects of Fan-In and Fan-out on propagation Delay and use of CMOS Transmission gates as switches.

Implemented the Real time clock using VHDL independently. Architect the verification environment using VHDL test bench.

Generated functional and code coverage for RTL verification and systhesized the design.

Designed a FIFO using fundamental logic gates and D flip-flops. Implemented the Control logic for the FIFO, and drew schematics using Cadence Virtuoso. Layouts were designed according to schematics.

Designed Data acquisition and implemented RTL design for Accelerator device and pro ASIC3E device using Libero IDE and VHDL.



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