Design Bus

CH ASWINI Email:***************@*****.***.

Ph. no:+91-910*******

CAREER OBJECTIVE:

I want to pursue a challenging career involving my technical, analytical, and interpersonal skills to give an outstanding performance to the organization with utmost dedication and commitment to the mission and vision of the team and the organization.

PROFESSIOAL SUMMARY:

Expertise in RTL coding using Verilog.

Good knowledge on System Verilog.

Good knowledge in Digital Logic design, ASIC Design Flow.

Have working knowledge on various bus protocols like AMBA AHB, AAP.

Worked with various tools - Xilinx, QuestaSim.

Very Strong in analyzing and debugging skills.

Individual contributor, good team player.

EMPLOYMENT DETAILS :

I have 1 year experience as a RTL Designer at NSRC Pvt. Ltd, Hyderabad.

TECHNICAL SKILLS:

Hardware Description Language : Verilog.

Hardware Verification Language : System Verilog.

Simulation Tools : QuestaSim

Synthesis Tools : Xilinx ISE

Protocol Knowledge : AMBA -APB,AHB, I2C.

Operating System : Windows

HANDLED PROJECTS:

PROJECT1:

TITLE: RTL DESIGN OF AMBA-ADVANCED PERIPHERAL BUS (APB) PROTOCOL

DESCRIPTION:- It provides a low-cost interface that is optimized for minimal power consumption and reduced interface complexity. The APB interfaces to any peripherals that are low-bandwidth and do not require the high performance of a pipe lined bus interface.

RESPONSIBILITIES:

Studied the specifications of AMBA-APB.

Involved in slave implementation.

Developed FSM based RTL module in Verilog.

Designed class based environment using system Verilog.

Developed Simulation tests for Testing for functionality of design.

Designed for single master and single slave environment.

PROJECT2:

TITLE: RTL DESIGN OF AMBA-ADVANCED HIGH PERFORMANCE BUS (AHB) PROTOCOL

DESCRIPTION:- AHB is a high-speed, high-bandwidth bus that supports multi-master bus management to maximize system performance. AHB serves the need for high-performance SOC as well as aligning with current synthesis design flows. AHB is a new generation of AMBA bus which is intended to address the requirements of high-performance synthesizable designs. This AHB Interface supports wider data bus, 32-bit address bus and Burst transfers to the AMBA Bus side.

RESPONSIBILITIES:

Understood the AHB Protocol Specification.

Designed the class based environment in System Verilog.

Developed Driver functionality for Master and Slave.

Developed Simulation tests for Testing for functionality of ddesign.

Designed for single master and multi slave enenvironment.

EDUCATIONAL DETAILS:

Course

Institution

Board / University

Year

Percentage /

CGPA

B.Tech (ECE)

Bapatla Womens Engineering

College,Bapatla

Acharya Nagarjuna

University

2017

8.1 / 10

Diploma (ECE)

Bapatla Polytechnic College, Bapatla

State Board Of Technical Education And Training

2014

81.54%

S.S.C

Z.P.H School, Vedullapalli

Board of Secondary Education, A.P.

2011

83.0%

PERSONAL DETAILS:

Date of Birth : 05 - 02 - 1996.

Marital Status : Single

Gender : Female

Language Known : English & Telugu

Relocation : PAN India

Declaration:

I do here by declare that the above information is true to the best of my knowledge.

Place : (Aswini)

Contact this candidate