Engineer Design

Curriculum Vitae

KARIMULLA SHAIK

Mob: +91-834*******

**.********@*****.***

POST APPLIED FOR :

CARRIER OBJECTIVE:

I am an enthusiastic and dedicated professional with extensive experience across all areas of technical system and engineering management. To be associated with a progressive organization that gives me an opportunity to seek a challenging career and to be a part of the team that dynamically works towards the growth of the organization.

STRENGHT :

Good analytical skills combined with a good sense of reality.

Well organized, dedicated & a good team leader.

Able to work with Multi- disciplinary team & confident achieving realistic target

ACADEMIC QUALIFICATION:

Post-Graduation in VLSI from BITS-Khammam in the year 2014 with 73.81%. with Distinction.

Graduation in ECE from Kakatiya University, Khammam in the year 2011with 65%.

Intermediate (M.P.C) from SMJC, Madhira in the year 2007 with 57.2%.

S.S.C from Ushodaya High School, Madhira in the year 2005 with 75%.

EXPERIENCE:

I work 8 months as a vlsi(associate) engineer in trylogic .

Now I am working Design and verification engineer in conscience technologies.

I took coaching in system verilog and uvm 4 months in Soctel technologies .

My present ctc 2.6 P.A.

Last working day:30/04/2019.

Expecting ctc:as per company nomes.

Current location :Hyderabad.

Project:ELECTRONIC VOTING MECHINE BY USING VERILOG CODE

Electronic Voting Machine is an electronic voting device used for conducting the parliamentary elections electronically. It consists of two units that can be inter-linked; a ballot unit which a voter uses to exercise his vote and a control unit which used by the polling officials. As there is no available design of Electronic Voting Machine using Verilog FPGA, in this paper, we introduce an efficient, transparent and secured FPGA implementation of EVM using Verilog HDL. The design is coded in Verilog hardware description language at Register Transfer Level (RTL).In thise design I used software Xilinx software.

Project:Adder verification in Systemverilog

In semiconductor design,design is major part after design we should verify the design also major part.in thise project I did adder verification for example In my design a and b are my inputs and sum and cary is my adder outputs. I randomize adder inputs and whater output we get compare in scoreboard .in score bord if results is math test will pass or result will miss match results is faill.

project:Memory verification in UVM

In thise project I did Normal memory verification here I take inputs and output as taransction level .and declare in class.after that we pass thise paket data to sequence in sequence paket data will be randomize .afer that pass a packet data to senqencer .and sequencer to driver pass data through tlm ports.afeter that pass data through driver to dut .after that monitor is convert signal level to pak leve after that pass data to scorebord in score bord it will chaek data is math or not.if data is mathch test will be pass or test will be miss match.

TECHNICAL SKILLS:

Programming Languages : Verilog HDL, System verilog,

UVM . C .

Working plate form : Xilinx, ModelSim, Queastsim.

PERSONAL SKILL AND EXTRA CURRICULAR ACTIVITIES:

Self motivated, active, punctual, always desire to learn and accept the new

Methods and techniques.

Other hobbies include Reading Book, Listing to Music, Playing Cricket, and Surfing Internet to gain the Knowledge.

PERSONAL INFORMATION:

Ø Father’s Name : Shaik uddandudad.

Ø Date of Birth : 15/06/1989.

Ø Marital Status : married

Ø Sex : Male

Ø Nationality : Indian

Ø Religion : Islam

Ø Languages : English, Hindi.

PASSPORT DETAIL:

Ø Passport No : P3425458

Ø Date of Issue : 26/07/2016

Ø Date of Expiry : 25/07/2026

DATE: PLACE:

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